ADSP-CM41x has up to 160KB of internal SRAM memory that may be used as CODE or DATA. This is allowed in 64KB chunks of SRAM that can be configured as either DATA or CODE at a time. However, this organization is only to facilitate performance, so that SYS Bus (DATA) and I/D Code buses (CODE) conflicts are avoided. Cortex M4 memory standard allows one to place CODE in DATA region and vice versa. This is supported in CM41x as well. This may come handy if user has to deal with small chunks of DATA that cannot be justified to occupy entire 64KB, which may better used to configure for CODE although with some memory allocated for DATA. This approach maybe used for CODE placement in DATA as well.