Synchronising multiple AD7768's to achieve simultaneous sampling of more than 8 channels

Document created by StuartADI Employee on Feb 12, 2016
Version 1Show Document
  • View in full screen mode

The AD7768 is an 8-channel, simultaneous sampling Σ-Δ analog-to-digital converter (ADC) with a Σ-Δ modulator and digital filter per channel, enabling synchronized sampling of ac and dc signals. The AD7768 achieves 108 dB dynamic range at a maximum input bandwidth of 110.8 kHz, combined with typical performance of ±2 ppm integral nonlinearity (INL), ±50 μV offset error, and ±30 ppm gain error.


The AD7768 also allows synchronized sampling to be extended across multiple AD7768 devices, which enables the user to synchronize sampling across many more channels within the system. For example, a user wishing to simultaneously sample up to 24 channels can easily synchronize across three AD7768 devices.


The AD7768 offers three options to allow ease of system synchronization. Choosing between the options depends on the system, but comes down to whether the user can supply a synchronization pulse that is truly synchronous with the base MCLK signal.

 

If the user cannot provide a signal that is synchronous to the base MCLK signal, one of the following two methods can be employed:

  1. Apply a START pulse to the first AD7768 device. The first AD7768 samples the asynchronous START pulse and generates a pulse on SYNC_OUT of the first device related to the base MCLK signal for distribution locally.
  2. Use synchronization over SPI (only available in SPI control mode) to write a synchronization command to the first AD7768 device. Similarly to the START pin method, the SPI sync generates a pulse on SYNC_OUT of the first device related to the base MCLK signal for distribution locally.

 

In both cases, route the SYNC_OUT pin of the first device to the SYNC_IN pin of that same device and to the SYNC_IN pins of all other devices that are to be synchronized. The SYNC_OUT pins of the other devices must remain open circuit. Tie all unused START pins to a Logic 1 through pull-up resistors.

 

If the user can provide a signal that is synchronous to the base MCLK, this signal can be applied directly to the SYNC_IN pin. Route the signal from a star point and connect it directly to the SYNC_IN pin of each AD7768 device. The signal is sampled on the rising MCLK edge; setup and hold times are associated with the SYNC_IN input are relative to the AD7768 MCLK rising edge.

 

In this case, tie the START pin Logic 1 through a pull-up resistor; SYNC_OUT is not used and can remain open circuit.


For more information search for AD7768 at: Search | Analog Devices

Attachments

    Outcomes