How is the Over-Range flag indicator set on the AD9625?

Document created by IanB Employee on Jul 21, 2015Last modified by IanB Employee on Jul 21, 2015
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What logic is used to flag overrange?  Just clipping?  Is one sample reading code 2048 enough, or is there some quantity that’s needed? 


For the over-range control bit that is embedded in the AD9625 output data stream, only one sample that is equal to 2048 is needed to show the over-range flag (can be many too).  The over-range control bit matches the over-range sample of interest.  This is true for +/- ADC Full Scale. In order to see the over-range indicator using 8L, 4L or 2L mode, the JESD204B over-range control bit needs to be enabled in the register: 0x72[7:6] = 01


In order to use the over-range control bit, you must be using either 8L, 4L or 2L mode of the JESD204B output data.  This allows extra bits of information to carry the control bit data in addition to the 12b of ADC sample data (i.e. N=12, N'=16)


In the 6L JESD204B mode, N=N'=12 and you will not be able to get any control bits in addition to the 12b of ADC output data. For 6L mode, the only option to detect an over-range is to use the “Fast Detect” (FD) method. This brings out an over-range flag earlier to a dedicated FD pin (sends it out in the middle of the ADC core).


The latency of the Ain-->FD will not match the Ain-->sample output, as it is “faster” than the JESD204B output. The fast detect method is described on page 28 of the datasheet and the registers of interest start at address 0x45. The FD feature also offers an adjustable limit and dwell time.


Ian Beavers