What are the tradeoffs in performance between the three power modes of AD7124-8?

Document created by JellenieR Employee on Jun 26, 2015Last modified by JellenieR Employee on Jun 26, 2015
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Q1.       What are the tradeoffs in performance between the three power modes of AD7124-8?

 

A1.       The part has three power modes – low power mode, mid power mode, and full power mode. In the full power mode, the analog input is sampled at 614.4 kHz. The maximum output data rate is 19.2 kHz. In this mode, the part has lowest rms noise for a given output data rate. It also has low offset drift and best PSR.

 

In the mid power and low power modes, the current consumption to some of the analog circuitry is reduced. Also, the master clock is internally reduced by 4 in the mid power mode and 8 in the low power mode. Hence, the sampling frequency being used by the modulator is reduced by 4 or 8 accordingly. This leads to considerable savings in the overall current. The reduction in current leads to increased rms noise, higher offset drift, and higher PSR.

 

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