FAQ: HMC Microwave Frequency Dividers by Analog Devices

Document created by MRichardson Employee on Jun 25, 2015Last modified by MRichardson Employee on Mar 17, 2017
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Question: Why should I consider using an Analog Devices Microwave Frequency Divider?

Answer: With the acquisition of Hittite Microwave Corporation, Analog Devices acquired one of the most comprehensive, microwave frequency divider product lines available on the market today. The product line covers input frequencies from near DC through 26GHz and includes fixed dividers with N values of 2, 3, 4, 5,and 8 as well as programmable dividers and counters with N ranging from 1 to 32 as well as a 48 bit Sigma-Delta fractional divider with sweep functionality! These are used for satellite, VSAT, point to point microwave radios and even test equipment applications all of which testify of their reliability, low noise and high performance.


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Question: What packages are these available in?

Answer: A multitude of options exist depending on the specific device. These are available in die, a hermetic package with leads (g8), a plastic package with gull wing leads (s8g), SOT26 as well as 3x3 (LP3), 4x4 (LP4) and 5x5 (LP5) QFN style packages.


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Question:  The website indicates that the device I need isn't available in die or in the package I need, what are my options?

Answer: Please contact the factory directly, depending on your needs and the business case we may be able to accommodate you.


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Question: Are these devices suitable for space applications?

Answer: Most dividers are based on GaAs technology which has proven reliable for space applications.


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Question: Are "leaded" or "non-RoHs" versions available?

Answer: Yes, please contact the factory directly for more information.


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Question: What is the ESD rating for these parts?

Answer: If it's not shown on the datasheet assume HBM Class "0" otherwise it will be listed on the datasheet.


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Question: What state will the output be in when for first clock cycle?

Answer: The output of the HMC digital frequency dividers is random.


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Question: Is there any way to have the divider power up in a known state?

Answer: No


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Question: Are these frequency dividers logic compatible?

Answer: Unfortunately, none of the HMC Frequency dividers are logic compatible. Because of this it's critical that the IO's are always DC blocked.


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Question: The datasheet mentions that the inputs must be DC blocked but there is no mention of this requirement for the outputs? Do I really need to DC block the output?

Answer: Yes, the outputs must be DC blocked as well. If you refer to the equivalent pin schematic in the datasheet you'll see that the output is taken directly off the collector off a transistor and there is no internal DC block. The applications circuit shown at the end of the datasheet will however always include DC blocking on the outputs. Please see the HMC394LP4E for an example of this.


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Question: After powering up the divider in my application I realized I forgot to install a DC block. Do you think I damaged the divider?

Answer: It depends on the load that was presented at the output and the specific divider being used. Generally speaking, you may have so it would be wise to install DC blocking and replace the divider.


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Question: What logic levels are used on the HMC divider products?

Answer: The IO's are similar to CML.


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Question: How will my load impedance impact the performance of the device?

Answer: The DC offset will remain at the same level regardless of the load. This is of course no concern since the output will be DC blocked. However, the peak to peak, output voltage swing will  vary depending on the load impedance. For instance, a device with operating into a very high impedance (10x greater than the internal impedance) will yield the full voltage swing that's available. A divider using an internal 50Ω resistor on the collector that is driving a 50Ω impedance will see 50% of the full swing.


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Question: So if these devices must be DC blocked why does the datasheet specify them as operating to DC?

Answer: Relative to the X, Ku and K  bands that these devices work up to, the low end of the band might as well be DC although technically it falls in the VHF region. As datasheets are updated, operation is being clarified to operate 'near DC'.


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Question: How low in frequency can I use these dividers?

Answer: Although specified to ‘DC’ most dividers will only work to ~40 – 50 MHz or so at drive levels near the upper end of the allowable range.


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Question: Are there any special considerations when operating near the low end of the dividers specified frequency range?

Answer: Below the specified 'typical' minimum input frequency, 100MHz in most cases, a square wave is required for reliable division. Additionally, the DC blocking capacitor values should be adjusted based on the frequency so that Xc is low (large value of capacitance). Finally, please consult the input sensitivity plot and be sure that the input power falls well within the 'recommended operating region'. Divider input sensitivity degrades at the high end of the band as well but more so at the low end so higher power will be required to maintain reliable division.


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Question: What is the minimum slew rate required for reliable division?

Answer: We haven't characterized these parts for this parameter.


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Question: Is there an easy way to estimate the slew rate?

Answer: Yes. Although it's always best to make the measurement, the slew rate can easily be estimated. The highest slew rate will occur at the maximum frequency. Simply divide the inverse of the maximum operating frequency by two to obtain the time it takes the signal to travel from the minima of the wave to the maxima during one half of the period (sine wave assumed). Next using the nominal output power and the characteristic impedance (typically 50Ω), derive the peak to peak voltage. For example a 15GHz signal driving 2dBm of output power into 50 ohms yields a time of 33.3pS and a peak to peak voltage of 0.796V so the slew rate would be 0.796V per 33.3pS.

 

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Question: Are rise / fall times available for these dividers?

Answer: We haven't characterized these parts for this parameter.

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Question: Is there an easy way to estimate the rise / fall time?

Answer: Yes. Although it's always best to make the measurement, the rise / fall time can easily be estimated. The fastest times will occur at very low frequencies which have much sharper edges and are more like a square wave. First, estimate the slew rate as shown in the previous question. Next, determine the peak to peak voltage that will occur at the maximum output power level and multiply this by the minimum rise time for ½ period at the maximum frequency (derived during slew rate calculation above). Finally, divide this result by the peak to peak voltage at the maximum operating frequency. Using the data from the slew rate example above and a maximum input power of 3dBm the Rise Time is ~(0.893Vpp * 33.3pS) / 0.796 = 37.4pS.

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Question: How were the parts characterized with respect to the data presented on the datasheet?

Answer: Unless specified otherwise all parts were characterized single ended.


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Question: Is there any difference in performance operating single ended vs. differentially?

Answer: No, the primary advantage is an additional 3dB of input power if operating at lower drive levels along with improved signal isolation vs single ended operation.


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Question: I'm operating near the lower end of the specified drive level and seeing un-reliable division is there anything I can do to improve this?

Answer: Operating at the extremes of the input drive level isn't recommended, however we have found that in some cases the use of the ATC Broadband 530L or Ultra-Broadband ATC550L capacitors for the DC blocking capacitors may help. Furthermore, if you're currently operating single ended and have the ability to migrate to differential operation this should help as the drive level will be increased by 3dB.

 

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Question: I prefer to operate the divider single ended, what's the best way to terminate the unused port?

Answer: On the input simply AC ground the unused port, for the output AC ground through a shunt 50Ω resistor.


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Question: I'm using the frequency divider single ended but for my layout it would be more convenient to use the NIN or NOUT pins instead of the IN or OUT pins? Will I get the same performance if I use these IO's instead?

Answer: Yes, the differential IO"s used on the HMC microwave frequency dividers are "truly differential" meaning that the only difference is the 180° phase shift.


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Question: How will the phase noise of my system be impacted by these frequency dividers?

Answer: Frequency dividers impact phase noise in 2 ways. The primary impact is simply a function of the frequency division itself. The phase noise of given application will improve at the rate of 20*LOG (N) where N is the division ratio of the divider. For a divide-by-2 case this results in a 6dB improvement. Unfortunately, nothing's free. The active devices in the digital circuitry degrade the phase noise slightly. This degradation is commonly referred to as 'residual' or 'additive' phase noise. This noise adds LINEARLY to the expected phase noise so the impact is more of a 2nd order type of effect. For example, the HMC433 operating with a 4GHz input at 0dBm specifies -150dBc/hz of residual phase noise at a 100kHz offset. Upon reviewing the plot you can see that this is only 10dBc/hz worse than what is shown at an offset of only 200hz! The practical result is that only offsets that are further out will be impacted. This is generally only a concern for applications operating with wide bandwidths.


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Question: . How can I determine the residual phase noise at my frequency of operation?

Answer: Residual or additive phase noise scales at 10 * LOG (Frequency), so if the desired frequency is double of the frequency at which the measurement was made there's a +3dBc/hz increase in the residual phase noise.


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Question: In my application I will not always have a signal present on the input of the frequency divider, will this cause any problems?

Answer: It depends on the device, some of the HMC devices are unstable when there's no input signal driving them. Fortunately there's a simple solution. Please refer to the link below to verify whether or not your application will be impacted and how to prevent the divider from becoming unstable when the input signal is not available.

 

Application Note: "Frequency Divider Operation and Compensation with No Input Signal" attached at the bottom of the following thread.

httpsRe: Self-oscillation of HMC434E://Re: Self-oscillation of HMC434ERe: Self-oscillation of HMC434Eez.analog.com/message/164809#


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Question: Are there any performance implications when implementing the recommendations outlined in the Application Note: "Frequency Divider Operation and Compensation with No Input Signal"?

Answer: If the recommended resistor values are used, there's only a minor impact to input sensitivity.


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Question: Can I cascade two dividers to obtain a division ratio that isn't offered?

Answer: Absolutely, there are a few things to pay attention to however. First, all IO's will need to be AC coupled, don't forget to optimize the value of the capacitor as the frequency cascades through the design. Secondly, the order matters. A divide-by-2 followed by a divide-by-3 is NOT equivalent to a divide-by-3 followed by a divide-by-2. While both scenarios may result in a divide-by-6 the former will have a duty cycle of 33% while the latter will have a duty cycle of 50%. The last divider in the chain sets the duty cycle. Finally, pay attention to the drive level requirements as the signal cascades through and choose dividers that keep the drive levels within the recommended operating range.


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Question: The 'Continuous Power Dissipation' value shown in the Absolute Maximum Rating table is higher than the device will ever see even if biased at the maximum levels, what's going on here?

Answer: The 'Continuous Power Dissipation' value is a 'theoretical' value based on the maximum continuous power dissipation that could be used and still maintain an MTTF of 1Mhrs. The continuous power dissipation at +85°C is derived by taking the maximum junction temperature (channel temperature) and subtracting the maximum operating temperature and dividing the difference by the thermal resistance (Rth). For example, on the HMC363s8g the maximum channel temperature = 135°C. This value is courtesy of the foundry and is the maximum channel temperature that the active device can operate at with a given current density that will result in an MTTF of 1Mhrs for the device. The maximum specified operating temperature is 85°C and the thermal resistance (Rth) is 73.2°C/W. This yields (135°C - 85°C) / 73.2°C/W for 683mW. If we ignore the RF contribution for a more conservative, result we see that the HMC363s8g will normally be operated at 5.0Vdc drawing a nominal 70mA of current. This is only 350mW; even at the maximum bias level we would only dissipate 394mW. This information can be useful in estimating the operating 'stress' levels when evaluating different devices. In this case, (ignoring temperature and RF contribution) the nominal operating stress would be 350mW / 683mW = 51.2% stress and worst case stress would be 394mW / 683mW = 56%. This reveals that the MTTF for this device would be much greater than 1Mhrs! This is further supported by the low maximum junction temperature at 85°C derived by multiplying our nominal power dissipation of 350mW x thermal resistance (Rth) = 73.2°C/W and adding the result to our maximum operating temperature (85°C) which yields 110.6°C; well below the 135°C maximum junction temperature.


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Question: What duty cycle should I expect to see at the output of these dividers?

Answer: The architecture of the divider circuit drives the duty cycle that will be present at the output. Generally speaking it's best to consult the datasheet for the frequency divider of interest. For dividers with a fixed divide ratio that is an 'even' integer value, the duty cycle will typically be 50%. Typically multiple divide-by-2' cores are cascaded to achieve the total divide ratio with the last stage setting the duty cycle. The HMC438 is a divide by 5 which has a typical 40% duty cycle. Programmable parts like the HMC794 or HMC905 have a 50% duty cycle regardless of the divide ratio while others like the HMC394 have a duty cycle that is inversely proportional to N. The HMC705 isn't quite as straight forward. If the dual-modulus prescaler could work all the way to 6.5GHz the duty cycle would simply be the inverse of "N". However, the '/2 or '/3 prescaler is required prior to routing the signal to the dual-modulus prescaler. This results in the percentage of the output duty cycle being derived for ratios from divide-by-3 through divide-by-17 equal to [(1 - 2/N) x 100]. Divide-by-1 is the same as the input and divide-by 2 is 50%. This architecture results in a unique benefit of having a minimum 33% duty cycle regardless of the divide ratio which means more output power is available even at the highest divide ratio.

 

While I'm discussing the HMC705 I should mention that in the bypass mode (divide-by-1),  the output waveform will be more square wave in nature except possibly at the high end of the band due to the signal passing through the various dividers and not simply being routed to the output divider.

 

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Question: What's the difference between a frequency divider, a frequency counter and  a prescaler?

Answer: While the terms "counter" and "divider" are often used interchangeably the counter typically includes a reset function to sync the pulses although this isn't the case with HMC counters; they typically employ a parallel architecture of cores whereas dividers often cascade cores in a serial manner. The HMC394 is a 5-bit programmable counter which can allow for either asynchronous or synchronous programming. The term prescaler is synonymous with a divider (or counter) used to divide down the input frequency of a subsequent stage so that it can be used as a functional block in a more highly integrated IC or module.

 

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