Will Boot streams generated for SPI master for SHARC+ core only boot on Power on Reset?

Document created by Harshit.Gaharwar Employee on Jun 15, 2015
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In terms of the Boot flow, in ADSP-SC58x, Cortex A5 is the primary core which does all the memory initialization and comes out of Reset on Power On reset. The other two SHARC+ cores remains in reset and it needs to be released out from Reset by the primary application running in Cortex A5.

So Single, Dual and Multi (All 3) core booting is supported in ADSP-SC58x.

But on Power On reset, the application written on ARM core will only boot.


So only below combined boot streams generated will boot in Power on reset:


  1. 1. Only ARM.
  2. 2. Arm and SHARC0/1
  3. 3. Arm, SHARC0 and SHARC1 combined boot stream


ARM needs to have a dummy application in case your application is only running in SHARC cores, to bring SHARC out of reset.

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