If an application enables XIP mode on the SPI flash (also known as continuous read mode) it puts the flash in a state where it is not expecting a command cycle instead it only expects an address.
After a System reset (SPI flash devices don’t have a reset pin), the flash remains in the continuous read(XIP) mode expecting an address cycle on the next SPI operation.
The ROM code will always issue a command cycle (0x03) to read the first nibble of the flash. So now the processor and the flash are completely out of sync. As a result of which the booting will fail.
So in order to boot such application it is the user’s responsibility to terminate the XIP mode of the flash and bring it back into the mode where it expects a command cycle.
This approach can be utilized in the application to make it work even via Booting.