How does the DMA (Peripheral and Memory DMA) view SHARC’s L1 memory?

Document created by Harshit.Gaharwar Employee on Jun 15, 2015
Version 1Show Document
  • View in full screen mode

All the DMA engines view SHARC’s L1 memory space from System View as Byte Addressable space.

For example SHARC0’s L1 Block 0 SRAM start address for a data byte access is 0x0024_0000.

In system view it corresponds to 0x2824_0000.

So the address passed to the DMA engine needs to be adjusted in the code by the user to take care of the Offset 0x2800_0000 for SHARC0’s core L1 internal memory.

Similarly for SHARC1’s L1 internal memory, an Offset of 0x2880_0000 needs to be passed to the DMA engine.

Attachments

    Outcomes