Is there a scenario which results in a pipeline stall when the SHARC+ core is accessing L1 memory?

Document created by MaheshN Employee on Jun 15, 2015Last modified by MaheshN Employee on Jun 15, 2015
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Yes , there are 3 scenarios where there is a pipeline stall for 1 cycle when the SHARC+ core is trying to access L1 memory (Instruction or data).


1. Conflict Cache miss on a PM data access

                  Eg:  R0 = PM(addr);

2. Two access to the same block in the same cycle

               Eg:  R0 = DM(Block0-addr1), background DMA to Block0

3. Conditional Store to any Load access

                  Eg:   If eq DM(A) = Fz;

                 Fa = DM(A/B);

All the above three sequences results in a single cycle stall .

Note that (1) and (2) was also present in the earlier SHARC core and (3) is the addition in SHARC+ Core .


The stall introduced when having two accesses to the same bank in the same cycle can be avoided by using different memory blocks will avoid . Similarly, the conditional store to load stall can be utilized by issuing any other instruction between the conditional store and the subsequent load.