How is the SPI peripheral different from the older SHARC processors?

Document created by vinodbableshwar on Jun 12, 2015
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1. The minimum PCLK to SPI_CLK ratio in SC58x is 1:1 which gives better granularity for baud generation.

2. The new SPI design supports flexible FIFOs, FIFOs are 8 deep for 8bit transfer size, 4 deep for 16 bit and 2 deep for 32 bit transfer size.

3. In older SPI design, the transfers has to be initiated with either read/write from/to receive/transmit FIFO, but newer designs allows flexible SPI transfer initiation. SPI can be configured to initiate transfer either when Transmit FIFO is not empty or Receive FIFO is not full or when both Transmit FIFO and Receive FIFO can accommodate new transfers.

4. The newer SPI also has word count registers, SPI will stop interrupting core after transfers equal to word count register is completed. In DMA mode, Word Count Register ensures that number of SPI transfers are exactly equal to value programmed in DMA channel.

5. The new design also support Urgent watermark, which is helpful in generating Urgent requests when transmit FIFO reaches near empty or receive FIFO reaches near full  levels.

6. The new SPI designs provides support for Hardware Flow Control. Flow control also support watermark feature which provides additional flexibilities.

7. The SPI on SC58x supports full duplex in DMA mode by providing separate DMA channels for transmitter and receiver.

8. New SPI design also supports Dual I/O mode ,Quad  I/O mode and Fast mode data transfers.

9. Apart from the legacy mode, SC58x SPI supports memory mapped mode and XIP modes.

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