How can I run the core clock at maximum of 450MHz and also source a 125MHz at the CLK07 for the EMAC TXCLK?

Document created by VineethaThomas Employee on Jun 10, 2015Last modified by VineethaThomas Employee on Jun 10, 2015
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CGU0 can be programmed to generate CCLK = 450MHz. The other CGU1 can be programmed to generate 125MHz that can be routed to CLK07 through CDU.

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