Is there any way that an Interrupt processing can be delayed in SHARC+ Core?

Document created by MaheshN Employee on Jun 9, 2015Last modified by MaheshN Employee on Jun 9, 2015
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Yes. There are certain uninterruptable sequences in SHARC+ Core. The earlier SHARC Core also had some un-interruptable sequences but due to its smaller pipeline , the number and length of such sequences were small.

An instruction is uninterruptible if the processor must execute it following execution of the immediately preceding instruction in the code. Processor ignores pending interrupts while executing such an instruction sequence.

 

The following are the un-interruptible sequences

  • During the start and termination of short loops encoded as F1 type .

    • Up to four instructions after execution of DO..UNTIL.

    • Up to nine instructions when loop terminates i.e., L-9 to L-1 instructions of unrolled short loop.

                    (Refer to PRM to learn about how this condition is mitigated)

  • Two instructions in delay slot of a delayed branch are uninterruptible.
  • The last but one instruction in arithmetic loop is uninterruptible during the last iteration of the loop.

 

Refer to the ADSP-SC58x Processor Programming reference manual for complete details

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