What is the minimum latency between a Core interrupt and the branch to the IVT?

Document created by MaheshN Employee on Jun 9, 2015Last modified by MaheshN Employee on Jun 10, 2015
Version 2Show Document
  • View in full screen mode

The processor responds to interrupts in three stages:

  1. Synchronization (1 cycle)

  2. Latching and recognition (1 cycle)

  3. Branching to the interrupt vector table (11 instruction cycles)

                   If the branch is taken from internal memory, the 11 instruction cycles corresponds to 11 core clock cycles. If the branch is taken from external memory, the 11 instruction cycles may span over many more clock cycles depending on the actual source of the instruction and the state and configuration of the system.

1 person found this helpful

Attachments

    Outcomes