Is the Interrupt Vector table in SHARC+ core same as that in SHARC core?

Document created by MaheshN Employee on Jun 9, 2015
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The Interrupt Vector table in SHARC+ core is not exactly the same as in SHARC Core. The various interrupts caused by external events on earlier SHARC processors has been replaced by the single SECI interrupt. All external interrupts will be managed by the System Event Controller (SEC) and this provides a single interrupt to the core

With the addition of new interrupts (for Parity error, Illegal opcode error etc), the number of interrupts have changed compared to earlier SHARC Core and hence the vector offsets has also changed.

Refer to the ADSP-SC58x Programming Reference Manual for various interrupts and their vector offsets.

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