In SHARC+ Core, does the external instruction fetch get cached in the Instruction Conflict Cache ?

Document created by MaheshN Employee on Jun 9, 2015
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In the SHARC Core of ADSP-214xx processors, all the external instruction fetch used to get cached in the Instruction Conflict Cache in addition to its main function of caching the instruction when there is a PMD bus conflict. Now this feature is depreciated in SHARC+ Core and only the PMD bus conflict instructions are cached in Instruction Conflict Cache.

The introduction of a separate L1 Cache Controller in SHARC+ core has taken care of caching any external instruction fetches.

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