How to select PSIZE and MSIZE fields of the MDMA configuration register on ADSP-SC58x/ADSP-2158x ?

Document created by Mitesh Employee on Jun 3, 2015
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Each DMA channel has two buses, one that connects to the SCB, which in turn is connected to the SCB slave (e.g. memories), and another bus that connects to either a peripheral or another DMA channel. The SCB/memory bus width can vary between 8, 16, 32, or 64 bits and is given by the DMA_STAT.MBWID bit field, while the peripheral bus width can vary between 8, 16, 32, 64, or 128 bits and is given by the DMA_STAT.PBWID bit field.

  • The DMA parameter DMA_CFG.PSIZE determines the width of the peripheral bus being used. It can be configured to 1, 2, 4, or 8 bytes. However, it cannot be greater than the maximum possible bus width given by DMA_STAT.PBWID. This is because burst transactions are not supported on the peripheral bus.

     

  • The DMA parameter DMA_CFG.MSIZE determines the actual size of the SCB bus being used. It also determines the minimum number of bytes, which will be transferred from/to memory corresponding to a single DMA request/grant. It can be configured to 1, 2, 4, 8, 16, or 32 bytes. If the MSIZE value is greater than DMA_STAT. MBWID, the SCB performs burst transfers to transfer the data equal to MSIZE value. It is important to understand how to choose the appropriate MSIZE value, both from functionality and performance perspective. The following points should be kept in mind when choosing the MSIZE value:

    1. The start address of the work unit should always align to the MSIZE value selected. Failing to do so will generate a DMA error interrupt.

    2. As a general rule, from a performance/throughput perspective, the highest possible MSIZE value (32 bytes) should be used for better throughput. This is because it results in a higher likelihood of uninterrupted sequential accesses to the slave (memory), which is most efficient for typical memory designs.

    3. From a performance perspective, in some cases, the minimum MSIZE value is determined by the burst length supported by the memory device. For example, for DDR2 accesses, the minimum MSIZE value is limited by the DDR2 burst length (4 or 8 bytes). Any MSIZE value below this would lead to a significant throughput loss.

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