How does the memory refresh operation in L2CTL memory system works on ADSP-SC58x/ADSP-2158x processors?

Document created by Mitesh Employee on Jun 3, 2015
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In order to make sure that the single-bit errors are not accumulated over a period of time thus reducing the chances of multi-bit errors, L2CTL provides a memory refresh mechanism for L2 SRAM.

Software can initiate a memory refresh cycle of a 64-bit SRAM entity by writing the address of interest into the refresh address register, L2CTL_RFA. The write triggers an atomic operation. In this operation,the L2CTL performs the following operations:

  1. Reads a 64-bit entity from the targeted memory,

     

  2. Applies an ECC algorithm to the two 32-bit words, and

  3. Writes the corrected data back to memory.

For more details, refer ADSP-SC58x/ADSP-2158x HRM.

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