How does the ECC error protection on L2 memory system works on ADSP-SC58x/ADSP-2158x processors?

Document created by Mitesh Employee on Jun 3, 2015
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For each write, the L2CTL memory system calculates and stores a 7 bit ECC value corresponding to the 32 bit data value. Whenever a read is made to an L2 memory location and the ECC protection is enabled for that particular bank, the ECC is calculated again. With the help of the new ECC value, the ECC hardware detects whether there is a single bit or multi-bit error.

  • If data in L2 SRAM contains single-bit errors, the data is corrected on its way to the system buses. The corrected value is not written back to the SRAM location.


  • The L2 controller flags 2-bit and multi-bit errors to the system by:

    1. Raising the ECC_ERR interrupt,

    2. Reporting a read error to the system bus,

    3. Setting the sticky L2CTL_STAT.ECCERR7—L2CTL_STAT.ECCERR0 status flag, and

    4. Latching the address of the failing operation into the respective L2CTL_ERRADDR7- L2CTL_ERRADDR0 register.

  There is one error status bit and one error address register per L2 SRAM bank. The interrupt service routine can consult the L2CTL_STAT register and the L2CTL_ERRADDR0 through L2CTL_ERRADDR7 registers to determine: 

  1. Whether the data at the failing L2 address was critical enough to require an immediate reboot of the system.

  2. Whether the data at the failing L2 address was less critical or can be restored.