What are the important features of the L2 memory system on ADSP-SC58x/ADSP-2158x processors?

Document created by Mitesh Employee on Jun 3, 2015
Version 1Show Document
  • View in full screen mode
  1. L2 memory system runs on SYSCLK domain. Thus it is slower than L1 memory.
  2. L2 memory serves as an ideal shared storage for multiple processor cores to share data, semaphores, sand code libraries. 

  3. L2 memory system offers data integrity protection with the help of ECC error detection/correction mechanism.Thus, it is also ideal for storing safety critical data and instructions.

  4. There are three instances of L2CTL on ADSP-SC58x/ADSP-2158x processors: L2CTL0, L2CTL1, and L2CTL2.

    • L2CTL0 contains 256K bytes of RAM grouped into eight banks, 32K bytes each and 32K bytes of boot ROM (ARM core).

    • L2CTL1 contains 256K bytes of application ROM grouped into eight banks, 32K bytes each and 32K bytes of boot ROM (SHARC core 1).

    • L2CTL2 contains 256K bytes of application ROM grouped into eight banks, 32K bytes each and 32K bytes of boot ROM (SHARC core 2).

  5. Each L2CTL controller has two ports: one 64 bit port for core accesses and one 32 bit port for DMA accesses. Both the ports can be accessed in parallel provided the accesses are made to different L2CTL banks.
1 person found this helpful

Attachments

    Outcomes