How DMC/DDR controller in ADSP-SC58x/ADSP-2158x different than DDR2 controller on ADSP-2146x ?

Document created by Mitesh Employee on Jun 3, 2015
Version 1Show Document
  • View in full screen mode
ADSP-2146x

ADSP-SC58x/ADSP-2158x

Supports only DDR2 memory devicesSupports DDR3, DDR2, and LPDDR memory devices
Supports maximum clock/data rate of 225/450 MHzSupports maximum clock/data rate of 450/900 MHz for DDR3, 400/800 MHz for DDR2 and 200/400 MHz for LPDDR modes
Has single instance of DDR2 controller but supports connecting up to four banks of DDR2 devices with the help of four separate chip select signalsHas maximum of two instances of DMC controller. For exact number of DMC controllers on a specific part, refer to the data sheet. Each controller supports connecting only one DDR3/DDR2/LPDDR device
The maximum DDR2 throughput is 800 MB/s (Mega Bytes per Second)The maximum DDR3 throughput is 1500 MB/s for writes and 1100 M MB/s for reads and DDR2 throughput is 1400 MB/s for writes and 1100 MB/s for reads
Supports DDR2 read optimization feature onlyHas a dedicated efficiency controller to provide advanced options to optimize the bandwidth such as page based scheduling, same master transaction scheduling,  read data buffer, auto-precharge option, SCB ID based priority, postponing auto-refresh commands etc
Supports multiple ODT and drive strengh options. ODT and drive impedance calibration is not supportedSupports ODT and drive imepdance calibration based on an external resistor DMC_RZQ

Attachments

    Outcomes