ADSP-SC58x is a complex chip with multiple core and diverse mix of peripherals. Some of these peripheral have very specific clocking requirements to function reliable or to meet specific application targets like SPDIF, DDR, MSI etc. and some of them need to be clocked as per the standards like PCIE, GigE modules.
Such a diverse mix of peripherals places a requirement to have a clocking scheme with enough clocks along with sufficient configurability to address the clocking needs of each module. To address this issue ADSP-SC58x/ADSP-2158x DSPs have dual CGUs (CGU0 and CGU1) so the number of avilable clocking options are effectively doubled. CGU0 acts as a primary CGU providing clocks to most of the peripherals and system busses.
To manage the routing of clocks from two CGUs to the target peripherals and different cores a clock distribution unit called CDU has been added to the chip. CDU is effectively a multiplexer which provides an option to route a clock to the target module(peripheral or core) out of four(maximum) clock options available for that given target. For following modules CDU provides an option to have a clock selected out of given options:
- SHARC (Core1)
- SHARC (Core2)
- Cortex A5 (Core0)
- S/PDIF Rx
For clock options available for each of these module refer to CDU chapter in HRM.
For an example use case refer to following discussion: Why do I need to configure CDU: Use case example?