Digital Lock Detect output from the ADF4106 is not indicating lock correctly, why?

Document created by Brigid.Duggan Employee on Dec 4, 2014Last modified by Brigid.Duggan Employee on Aug 10, 2016
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The ADF41XX family of integer –N PLL synthesizers offer two forms of lock detect: Analog Lock Detect ( ALD) and Digital Lock Detect ( DLD). The AN-873 application note explains both options to allow the user to make an informed decision as to which form of lock detect to use.

The Phase Frequency Detector (PFD) produces outputs UP and DN in response to the frequency and phase difference at the inputs, namely the R counter and N counter outputs. The logical NOR of UP and DN is used as the source signal for both the ALD and DLD circuits.

Figure 1. PFD and Charge Pump on the ADF4xxx Family of PLL Synthesizers

The logical NOR of the PFD outputs in a locked state produces a logic high with low pulses, whose duration is set by the anti-backlash pulse width plus any additional leakage currents.


Figure 2. Timing Diagram of PLL in Lock Showing the Reference Signal, Divided RF Signal, Q1 and Q2 (the Up and Down Pulses Going from the PFD to the Charge Pump), and the ALD Signal, which is the NOR of Q1 and Q2


Leakage currents can have a number of sources, most prominent are, VCXO’s, the charge pump, loop filter capacitors, and biasing currents for active loop filters.

After filtering, ALD can have more than just a 0 or 1 representation of a PLL lock status. The output voltage level can more accurately portray the lock status, however, the filter must be designed carefully, and the rise and fall times of the output voltage level can be an issue in some applications. ADIsimPLL can be used to design the ALD external filter components.

Digital lock detect is a CMOS logic output, whose status is logic high for a PLL lock.  By its digital nature, DLD has to make a definite yes-or-no decision as to whether or not a PLL is in lock. Under certain circumstances, as described in application note AN-873, DLD is susceptible to inaccuracies. Through careful consideration of the PFD frequency and leakage currents flowing, it is possible to determine if DLD is accurate in a particular application.

The Digital lock Detect circuit uses the logical NOR of the PFD outputs as its CLKIN source.

Figure 3. Simplified Circuit Diagram for Digital Lock Detect; CLKIN is the Analog Lock Detect Signal


As mentioned, this signal will have low going pulses, whose width will change depending on the anti-backlash pulse and leakage currents. In fact, the leakage currents act to increase the pulse width from its nominal value (which is the anti-backlash pulse width).

The Digital lock detect circuit uses a set window of 15nsec pulse width to determine the lock status of the PLL. When CLKIN of the DLD circuit has a pulse width of less than 15nsec for 5 consecutive cycles, the DLD circuit indicates that the PLL is locked.

Once the DLD circuit indicates lock, it now looks for a loss of lock. The loss of lock is detected when the pulse width of the CLKIN to the DLD circuit is equal to or greater than 30nsec on any subsequent PFD cycle.

In applications where the leakage currents are large enough to increase the pulse width duration of CLKIN to greater than 15nsec, then DLD will not be able to indicate lock, even if the PLL is locked. In this case, the use of ALD is necessary.

The set window for digital lock detect and loss of lock does not change over the usable PFD frequency change. Therefore it’s obvious that the accuracy of the digital lock detect is a function of the PFD frequency. The higher PFD frequency, the shorter will be the periods of the R counter and N counter signal to the PFD.

Taking an example of a PFD frequency = 30MHz, the R and N counter periods will be equal to approximately 33nsec. In this case the accuracy of the digital lock is compromised as the unlocked frequency close to the desired frequency will cause the CLKIN feeding the DLD circuit to drift in and out of the 15nsec window. In this scenario the DLD signal will pulse high and low. In a more extreme case, using a PFD=100MHz, will result in signals at the PFD with a period of 10nsec. A frequency error in this application of 10 % would put the two PFD inputs within 1nsec of each other and the DLD will inaccurately indicate lock detect. In this application it is necessary to use ALD instead of DLD to indicate lock.

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