AD7175-2 250kSPS, 24-bit Sigma Delta ADC FAQ

Document created by RobK Employee on Nov 25, 2014
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Q1. How do I interface to the ADC?

A1. The AD7175-2 uses an 3 or 4 wire SPI interface.

 

Q2. Can the part be used with CS tied low?

A2. Yes. However, using the AD7175-2 with CS tied low makes the interface less robust to interference and can cause loss of interface synchronization.

 

Q3. I’m not sure if my digital interface is working – how can I check this?

A3. The ADC has a read-only ID register which will always read back as 0x0CDx.

 

Q4. I don’t see a reset pin – how do you reset the ADC?

A4. The AD7175-2 does a power-on reset but can also be reset by writing 64 1’s to the part over the SPI interface.

 

Q5. Are there any precautions that should be taken to make the interface

more robust?

A5. The AD7175-2 has optional CRC protection for the interface so turning this on will make the interface more robust. Using CS will also make the interface more robust as when CS goes high the serial interface is set to a known state and any interference whilst CS is high will be ignored.

 

Q6. What does the MUX_IO bit do?

A6. The MUX_IO bit enables the AD7175-2 GPIOs as external multiplexer control lines. GPIO0 and GPIO1 will toggle in synchronization with the ADCs internal sequencer.

 

Q7. Is it possible to control the conversion start similar to using CONVST on a SAR ADC?

A7. Yes, the AD7175-2 has a SYNC input which can be used to control the conversion start.

 

Q8. There are a number of filter options – which one should I use?

A8. The AD7175-2 has three filter options; Sinc5+Sinc1, Sinc3 and enhanced 50 & 60 Hz filters. The Sinc5+Sinc1 is most suited to multichannel applications where fast multiplexing is required. The Sinc3 is best for single channel applications running at lower output data rates. In applications where rejection of 50 and 60 Hz is important the enhanced 50 & 60 Hz rejection filters should be used as they provide better performance that the Sinc filters and allow the user to trade off settling time or rejection to meet their application needs. We provide a  filter tool to help during  design in: see www.analog.com/AD7175-2

 

Q9. The AD7175-2 has a maximum output data rate of 250 kSPS but a channel scan rate of 50 kSPS / channel. What does this mean?

A9. When operating on a single channel the AD7175-2 can output data at up to 250 kSPS. However, when more than one channel is enabled the full filter settling time must be allowed for each channel. The data rate for fully settled data is 50 kSPS. So, if using 2 channels the output data rate for each channel is 50 kSPS / 2 which is 25 kSPS.

 

Q10. Can the ADC be configured to settle in a single cycle ?

A10. Yes, setting the SING_CYC bit will allow this. It should be noted that the Sinc5+Sinc1 filter will settle in a single cycle at output data rates of 10 kSPS and lower regardless of whether the SING_CYC bit is set or not.

 

Q11. The AD7175-2 has integrated truly rail to rail analog input and reference input buffers. What advantage do these have over normal RRIO buffers ?

A11. Normal rail to rail input/output (RRIO) buffers can often degrade in their linearity performance when they get close to the rail. The AD7175-2 buffers are truly rail to rail meaning that this degradation does not occur. In addition, these buffers are chopped and so have excellent offset performance and no 1/f noise profile.

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