FAQ: ADIS162xx LGA Assembly Guidelines

Document created by NevadaMark Employee on Oct 18, 2014
Version 1Show Document
  • View in full screen mode


In addition to the standard JEDEC guidelines, J-STD-020 (solder reflow) and J-STD-033 (moisture sensitivity), do the ADIS162xx LGA devices have any other requirements for installation on to my PCB?



J-STD-020 and J-STD-033 apply to single-die packaging, which leverage materials that support support exposure to temperatures of up to +260C.  The ADIS162xx device are system-in-package (SIP) solutions, which include a wider set of components and assembly materials.

Some of these materials present elevated yield risk when the temperatures exceed +240C and or when the devices experience moisture ingression prior to solder re-flow assembly. 


Moisture ingression prior to solder reflow. All of the ADIS162xx LGA devices have passed qualification testing for the MSL5 rating, per JEDEC J-STD-033. In serving a broad, diverse market, we have found that while ADI testing and characterization of MSL5 has proven successful, the ADIS162xx LGA package style can have a little more sensitivity to process variation, with respect to moisture ingression risk, when compared to typical companion devices.  Therefore, ADI recommends the following process step for the ADIS162xx devices:

Solder-reflow time/temperature profile.  The ADIS162xx package style and size fall under the +250C peak temperature requirement, per JEDEC J-STD-020C. Due to the sensitivity of some materials used inside of the ADIS162xx LGA devices, ADI recommends that the peak temperature, at the site of the ADIS162xx LGA device, not exceed +240C during solder reflow.  All other temperature reflow guidelines, per JEDEC J-STD-020.

Peeling stress can cause device leads to fracture. This is a common sensitivity for LGA and BGA packages, but the ADIS162xx LGA devices have a bit more sensitivity to this than typical companion devices.  The reason for this sensitivity is due to the rigid packaging materials, which support best sensor performance metrics when experiencing changing stress profiles from the PCB.  A common cause of peeling stress is PCB separation techniques, which causes the PCB to bend and places the lead interfaces in "tension." Cracks in these lead interfaces can cause poor yield and premature failures in service, so this is an important consideration.  There are two parts to managing this risk: optimize lead strength and protect the leads from peeling stress. Here are tips in optimizing the solder joint quality:

Protecting the leads can involve the following:

    • ADIS16xxx boards (such as ADIS16209/PCBZ) use a rotating bit to cut boards out of the arrays, after the solder reflow step.
    • PCB design: break-point size, break point proximity to ADIS16xxx device, mounting hole location, thickness, width, length and material rigidity; along with device proximity to natural bend points, can impact exposure to peeling stress.
    • Clamp PCB ends during separation
    • Use of an underfill compound to help distribute peeling stress across the entire bottom of the package. The following materials, provided by Hysol, have been used with success: FP4470, FP4545FC, FC4502, and FP4548.  The following tips may help in developing an under-fill process:
      • Pre-heat the PCB to +90°C, to help the material whick under the ADIS16265's package bottom.
      • Deposit under-fill material on two adjacent edges of the ADIS16265 and allow the material to wick under the package, for approximately 30 minutes
      • Bake at +125°C for 30 minutes to help the material set
      • Bake at +160°C for 90 minutes to fully cure the material