ADF41XX REFIN Signal Characteristics

Document created by Brigid.Duggan Employee on Aug 11, 2014
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What drive level is acceptable for the REFIN input?

The signal level for REFIN is specified in our datasheets to have a voltage greater than 0.4Vpp or 0.8Vpp, and less than VDD, biased at VDD/2. The REFIN  input circuitry OF THE ADF41XX is biased at Vdd/2.

·         When the REFIN source and ADF41XX share a supply voltage, the REFIN signal can be connected directly.

·         When the REFIN source and ADF41XX do not share a supply voltage, the REFIN signal should be AC-coupled; typically a 1 nF capacitor is recommended.


For, best performance, does REFIN of ADF41XX accept both signals of sine wave and square wave?

REFIN can be a square wave, a pure sine wave or a clipped sine wave, but must meet the datasheet requirements in terms of REFIN Sensitivity, REFIN Frequency/Slew rate and nominal threshold of VDD/2.

The following circuit note uses high speed clock buffers to extend the low frequency of a high performance phase locked loop( PLL).

To get the best performance in terms of phase noise/spurs from the ADF41XX a very clean reference source is required. With reference to the ADF41XX datasheet, our phase noise, figure of merit and spurs are all carried out using a very clean reference source. While this may not be practical in a real world application, it shows the performance of our part without significant noise from a reference source.


I'm trying to determine the type of clock I can use for the REFIN of an ADF41XX.  The data sheets states that it is a CMOS input with threshold of VDD/2 and can be DC or AC coupled.

The choice between providing a DC-coupled, CMOS compatible square wave or AC-coupled clock signal depends on the available REFIN.  – for example,  if your reference signal is a 10 MHz sine wave signal, and meets the minimum requirements for Sensitivity and Slew rate, then you can simply AC couple to REFIN.

However, if you have an option to apply a square wave reference signal with sharp edges, you might consider it – increasing the slew rate of the falling edge of the reference signal can improve the phase noise of the part.



What is the sensitivity of the ADF41XX to duty cycle of REFIN?

REFIN is specified in the datasheet to have a maximum frequency. For example, the ADF4106 REFIN is specified to have a maximum frequency of 300MHz. This implies that the REFIN operates with a minimum pulse width of 1.6nsec (50/50 duty cycle). Therefore, as long as the pulse width of REFIN does not go below 1.6nsec when driving REFIN with duty cycles of less than 50%, then operation with low duty cycle REFIN signals are acceptable.