FAQ: CPLB enhancements in Blackfin+ Core

Document created by ColinJ on Jul 24, 2014Last modified by ColinJ on Aug 1, 2014
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1. CPLB default MMRS
New MMRs are added to take specific default action when data or instruction CPLBs are missed. A default cache mode, memory properties, access restrictions can be programmed in CPLB default registers. When a CPLB is missed for a specific memory region, these default properties are considered for that memory region. This new feature eliminates the need of covering entire memory region with CPLBs.
2. Implicit CPLBs
MMRs are not required to be covered by CPLB entries. MMR access will always be permitted in supervisor mode and always cause an illegal use of supervisor resource exception in user mode.
Scratchpad memory(L1 Databank C) has to be covered by CPLB entry just like L1 data memory.
3. CPLB Data registers
The DCPLB and ICPLB Data registers now contains CProps field which decides cacheability property of  memory page. CProps  is 3 bit field in L1_DM_CPLB_DATAn(Data memory CPLBs) and  2 bit field in L1_IM_CPLB_DATAn.Cprops replaces the CPLB_WT and CPLB_L1_CHBL bits of L1_DM_CPLB_DATAn and CPLB_L1_CHBL bit of L1_IM_CPLB_DATAn of  older Blackfin implementation .

A new cacheability property called I/O Device Space is introduced for data memory page(L1_DM_CPLB_DATAn) in Blackfin+ core. The processor will not issue speculative accesses to memory with the I/O Device Space property. This new feature will fix the problems caused by  speculative fetches when FIFO type  type devices are interfaced with the processor.
4. CPLB Dirty Bit
     A protection violation exception will be generated on a store to a page with a zero Dirty bit irrespective of the memory properties.
5. CPLB page size
In new Blackfin+ core, Additional page sizes of 256K , 1M, 256M, and 1G are supported in CPLB page size
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