FAQ: Enhancements in Supervisor Mode in Blackfin+ core

Document created by ColinJ on Jul 24, 2014Last modified by ColinJ on Aug 1, 2014
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1.Supervisor Access bit

The new Blackfin+ core support entering supervisor mode through setting SACC(supervisor Access bit ) bit of SYSCFG register. When the SACC bit is set , processor allows supervisor access even when not servicing interrupt or exception. When SACC bit is cleared , supervisor access is permitted only when servicing interrupt or exception. Hence processor will be in supervisor mode ,When servicing an interrupt, a nonmaskable interrupt (NMI), an exception, or when  SACC bit is set .This new feature will remove the restriction on  supervisor access only when servicing interrupt or exception.


The User Stack Pointer (USP) register will  be used when not servicing an interrupt, a nonmaskable interrupt, or an exception irrespective of the mode.


2.Making the IDLE instruction supervisor only

 

The IDLE instruction can be made supervisor only by setting STRICT bit of SYSCFG register. If IDLE instruction is executed in USER mode ,exception will be generated. This will help in improving user mode security in RTOS based system.

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