FAQ: Performance Enhancements in Blackfin+ core

Document created by ColinJ on Jul 24, 2014Last modified by ColinJ on Aug 1, 2014
Version 2Show Document
  • View in full screen mode

    There are several new features in Blackfin+ core. Some of the Key features which greatly improve performance over existing Blackfin is listed below

 

  1. Posted system MMR writes

The Blackfin+ core supports posted MMR writes.This feature can be enabled by setting MPWEN bit in SYSCFG register. 

When Posted MMR write is enabled,

  • Core does not wait for a system MMR write to complete before starting another system MMR write.
  • The core does not ensure writes complete in correct order. But system infrastructure will ensure that these writes will complete in the correct order.
  • Core waits for all system MMR writes to complete before issuing a system MMR read. So loads from system MMRs may take longer.


2. Dynamic Branch prediction

    The Blackfin+ core supports dynamic branch prediction. BPEN bit in the SYSCFG register enables the Dynamic Branch prediction. When dynamic Branch prediction is not enabled Static branch prediction is used for predicting branches.


3.16-bit complex multiplication

The Blackfin+ core has new instructions which support 16 bit complex multiplications. The instructions support multiplication of A * B  , A * B’ and A’ * B’ . Where A and B are complex numbers and A’ and B’ are complex conjugate of respective complex numbers. These instructions greatly improve performance of algorithms which involves complex multiplications.


4. Single Cycle *= Multiplication


        *= instruction takes single cycle to complete in Blackfin+ core.

 

5. 32 bit multiplication

    New 32 * 32 = 64 bit multiplication instructions which support optional saturation and rounding are available.

 

6. Add with carry and Sub with borrow

New Add with carry and Subtract with borrow with optional saturation instructions are available.


7. Shift instructions

    New Assembly Syntax for Arithmetic right shift with saturation and Arithmetic Left shift are added into new Blackfin+ core

 

Assembly  Syntax

 

REG = REG <<< IMM

REG = REG >>> IMM (s)

 

8.   Not cc to Data register

A new instruction  which enables copying !CC value to Data Register is added.

 

Assembly Syntax

REG=!CC

 

This instruction leads to small improvements in compiler generated code as it directly provides a way to copy the inverse of CC value to Data register.


9.Load immediate 32

     In Blackfin+ core ,the immediate 32 bit value can be loaded into Data registers(R register),Pointer registers( P registers, SP,FP), Index  registers(I registers), Modify registers(M register),Length registers(L registers) and Base registers(B registers)


10 .Absolute address Load/Stores

   Load and store from absolute 32 bit address is supported in the core.


11.   Jump/Call to immediate 32

The older Blackfin core allows only 25 bit PC relative address, but in the Blackfin+ core ,Jump and Call can use immediate 32 bit value for PC relative address.


12.    P addressed Load/Store in DAG slot 2

In Parallel instructions, The restriction that if the two 16-bit instructions are memory access instructions only one can use the P-registers as an address register is removed.


13.   TESTSET instruction

In Blackfin+ core, TESTSET instruction can be addressed to any memory byte. These are not cache inhibited access. TESTSET  to cacheable memory region checks cache and update the data in cache.

 

14.   Scratchpad Memory is same as other L1 data memory

           Blackfin+ core allows DAG and DMA access to scratchpad memory. Hence Scratchpad memory is available to user just as other L1 Data banks.

2 people found this helpful

Attachments

    Outcomes