Q: How many GPIOs are available in ADuCM350?
A: Up to 66 depending on peripheral function use. Each GPIO can be configured as an input or an output.
They also have internal pull-up or pull-down programmable resistors. All I/O pins are functional over the full supply range (VBAT = 1.8 V to 3.6 V), and the logic input voltages are specified as percentages of the supply.
Q: Can the LCD segment driver pins be configured as GPIOs?
A: Yes. One important note is that these pins are on the VLCDVDD supply domain. When the segment driver is not being used, the VLCDVDD pin should be connected to VCCM in order to power the P1.X and P2.X GPIO pins. See LCD Charge Pump and External Capacitor Requirements section of the ADuCM350 Hardware Reference Manual (UG-587).
Q: How do I mux different peripherals on the GPIO pins?
A: A Pin Multiplexing application (PinMuxUI) is provided as part of the Software Development Kit (SDK) which is capable of generating code to set all of the port MUX and FER registers statically for all peripherals in a single call. Further information can be found in the the Build Configurations chapter of the ADuCM350BBCZ Software User's Guide. The application can be found in the tools directory of the SDK installation.
Q: Can I use P1.7 (CLKOUT) as a Clock Source for an external device ?
- Pad B8 (P1.7/S10/D7) is always supplied by VLCD rail, regardless if LDC logic is enabled
- Pad mux can be changed from LCD to GPIO, PDI or CLKOUT
- VLCD rail supports 2 use cases: direct connection to battery (VCCM) and generation from internal charge pump
- If enabled, the VLCD charge pump can continuously deliver 200 uA (2.4V to 3.6V)
- If GPIO or alternate pin function is enabled while LCD charge pump is enabled, the following limitations apply:
- VOL/VOH and VIL/VIH will track VLCD supply – datasheet specs are not applicable in this operating mode
- I/O drive strength as described in datasheet is not applicable in this operating mode
- Drive strength register should never be set high in this operating mode
LOAD Considerations If Using LCD and P1.7 for Clock Source
- Multiplexed mode can drive up to 32 FP and 4 BP = 128 Segments, but only 32 are driven at a time and FP – BP < VLCD
- Worst case is static mode: FP – BP = VLCD
- VDC (average) = 0 VDC
- Vrms = VLCD
- Worst case refresh ratio = 80 Hz
- Worst case capacitance of a segment = ~130 pF
- Segment impedance has no resistive component; only reactive:
- Z=X_C=1/((2πfC) )=1/((2π×80×130E-12) )=1.53E+7Ω
- Maximum 32 segments: 32×196nA=6.3uA
- VLCD load due to LCD glass is negligible
Headroom Analysis (assume external device requires 32kHz clock)
- To allow sufficient headroom for corner cases, avoid continuous load on VLCD > 100 uA
- Current available for Device Clock ~ 100 uA
- Minimum resistive divider: R=V/I=(3.0V)/100uA=30K
- Adding a resistive divider to clock output creates an RC network with External Device clock circuit input capacitance
- Cutoff frequency 〖=f〗_c=1/2πRC
- Use lowest value resistive divider allowed given current available
- If R=30K, then f_c=1/((2×π×30000×50E-12) )≅106kHz
- f_c>3X External Device Clock
- If LCD contrast (adjustment of VLCD bias) is used, equations in headroom analysis must be adjusted
- If VLCD bias is adjusted, VOL/VOH will track and may have implications in RC network created by voltage divider and External Device clock input capacitance
- Temperature and process variations in resistive divider may influence effective jitter on clock output signal used for External Device
- Pad B8 (P1.7/S10/D7) configured as CLKOUT will not operate when the device is in hibernate (DEEPSLEEP)