Powering Analog circuit through SMPS.

Document created by LucaV Employee on Dec 18, 2013Last modified by LucaV Employee on Apr 2, 2014
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SMPS output has ripple and switching noise at its output. Such a supply could hamper performance of high resolution slow speed analog circuit.How to reduce it? A low noise linear regulator would do? An LC filter can work or both( LC filter followed by linear regulator)? A ferrite bead is also a general practice."Please suggest me how should i power my slow speed high resolution analog hardware(i am talking about process control, mainly temperature measurement applications)".


This is a very interesting topic and one that's hard to answer in a few lines of text.

First you should look at the datasheets of the part you are using to identify if there is a recommended power solutions, then identify the PSRR curves in the datasheet if they are available.

As a general rule if you signal of interest is in <100Khz most part have very good PSRR and the power domain does not need to be extremely clean. For parts with much higher bandwidth and signals in the 1Mhz to 1Ghz then noise from the power supply needs to be managed in multiple ways, filtering and LDOs.

If you are dealing with parts that are sensitive to noise at any frequency such as PLLs and VCOs then everything needs to be designed with low noise in mind.

 

We have some design examples in what we called the circuits from the lab section of our web site

http://www.analog.com/en/circuits-from-the-lab/CN0147/vc.html

http://www.analog.com/en/circuits-from-the-lab/cn0201/vc.html

http://www.analog.com/en/circuits-from-the-lab/CN0234/vc.html

http://www.analog.com/en/circuits-from-the-lab/CN0183/vc.html

 

Finally I recently recorded a session for ADI's Virtual Conference DC-13 that addressees exactly this topic.

 

Powering Noise Sensitive Systems
When it comes to high performance signal chains, you need high performance power solutions. Noise sensitive circuits such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and phase lock loops (PLLs)—as well as FPGAs—demand low noise power supplies that require specialized design techniques. Engineers spend hours trying to figure out how to power these circuits without adding noise. This presentation will focus on understanding various methods for not only approaching but meeting system requirements. The session will introduce tested solutions and layout considerations that must be taken into account when designing with switching regulators and low drop out (LDO) regulators.
Presented by: Luca Vassalli, Power Management Applications Manager

 

This FAQ was generated from the following discussion: Powering Analog circuit through SMPS.

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