TDD Mode Switching Time

Document created by PWiers Employee on Nov 14, 2013Last modified by PWiers Employee on Mar 13, 2017
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There are several modes in the AD9361 that can address TDD applications and it is important to pick the most effective mode for the application at hand.  The ENSM and PLL sections of the user guide describe TDD switching as well.  The ENSM guide also explains the SPI and the pin-control methods for controlling the ENSM and the LO.

 

 

Several factors affect how quickly the AD9361 can switch from Rx to Tx and vice versa including:

 

  • The RF VCO calibration duration which is dependent on the scaled reference clock frequency.  Higher frequencies result in faster calibration times as described in the PLL user guide.  The time is always greater than 37us.
  • RF PLL lock time of approximately 15 us, regardless of clock rates.
  • Rx and Tx flush, described in the ENSM user guide and is dependent on the ADC clock.
  • Tx DAC power up time is approximately 18us regardless of configuration and only affects switch time when moving to the Tx state.
  • Signal path latency is dependent on clock rates and filter configurations which can vary greatly.  It always must be accommodated so it not delineated in the methods below.

 

The Rx to Tx or Tx to Rx maximum switching time is different for each of the modes described below.  Knowing the maximum time allowed by the application helps determine the best option.

 

  • Standard ENSM TDD Mode: VCO calibrations occur as the ENSM moves among its states and it is not possible to enter the Rx state while the Rx PLL is unlocked.  Similarly for the Tx state and Tx PLL.  After the calibration, the PLL locks.  Tx DAC power up time (if changing to Tx) and flush time also need to take place but these can occur in parallel with the PLL switch.  Standard ENSM TDD mode is usually dominated by the VCO calibration time.
  • Standard TDD mode/No VCO cal: This option uses the TDD ENSM mode but doesn’t allow RF VCO calibrations when the ENSM switches states. In order to make sure the PLLs don’t unlock at some future time, the VCOs should be calibrated during initialization using the most accurate mode and should enable temperature compensation, both of which are used in the FDD mode.  Thus, the AD9361 would be initialized as if for FDD mode.  At the end of initialization, the ENSM would be moved to TDD mode and the VCO calibration would be disabled by setting bit D0 of 0x230 and 0x270 high.  This method would be shorter than the method above by the VCO calibration time.
  • Standard TDD mode/Dual Synth: In this case, the Dual Synth bit is set, enabling both PLLs and eliminating the PLL lock time (and the VCO calibration).  When switching to the Tx state, the Tx DAC must still power up and the flush times must still occur.  Similar to the method above, the AD9361 should be initialized as if for FDD mode.  The VCO calibration does not need to be disabled.
  • FDD Independent Mode: This configuration calibrates the AD9361 as if normal FDD mode would be used but allows the Rx and Tx paths to be enabled and disabled independently so there is infinite freedom in the timing of the Rx and Tx data paths.  The ENSM user guide describes this operation in more detail and the signals used.  The ENSM does not change state so the digital paths do not flush.  However, the Tx DAC still powers up and down along with the rest of the Tx signal path.
  • Standard FDD mode enables both LOs both data paths.  Since the Tx path is always on, LO leakage can couple back into the receiver through an external switch or duplexer which can degrade performance.  This mode would only be used if none of the ENSM TDD modes would work and if there was not sufficient flexibility in the baseband processor control signals to use the FDD Independent mode.
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