[#6671] urjtag reset should have option to work around bf526-0.0 bootrom bug

Document created by Aaronwu Employee on Oct 17, 2013
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[#6671] urjtag reset should have option to work around bf526-0.0 bootrom bug

Submitted By: Mike Frysinger

Open Date

2011-06-30 00:44:26    

Priority:

Medium     Assignee:

Jeff Bartlett

Chad Wentworth

Jie Zhang

Board:

N/A     Silicon Revision:

0.0

Resolution:

Assigned (Not Started)     Fixed In Release:

N/A

Processor:

BF526     

Host Operating System:

toolchain rev.:

    kernel rev.:

State:

Open     Found In Release:

snaps

Is this bug repeatable?:

N/A     

Summary: urjtag reset should have option to work around bf526-0.0 bootrom bug

Details:

 

the bf526-0.0 has a known bug in its bootrom where it hangs if the software reset bit is set in the SWRST register.  the way to workaround this is to clear that bit.  normally that's done by simply reading the SWRST MMR.

 

unfortunately, this doesnt work when executing in emulation mode (EVT0).  the core needs to run at a lower EVT level in order to have the read implicitly clear the bit.

 

so the workaround would:

- see if this is a BF52[246]-0.0 CPU

- save current PC

- save some bytes at the start of L1 inst SRAM

- write start of L1 inst SRAM with code that reads the SWRST and does emuexcpt

- release the processor from emulation mode so that it executes the code

- restore the bytes at the start of L1 inst SRAM

- reset PC to previous location

 

since this is a bit complicated, we'll probably want to make it an option

 

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