2011-02-25 20:14:06     Micro-Architecture Information

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2011-02-25 20:14:06     Micro-Architecture Information

Hamed Tabkhi (UNITED STATES)

Message: 98443   


Hello Mike,


I am PhD student at Northeastern University working under Prof Schirner. As I  have already told you, I am trying to implement a more accurate simulation model for core of Blackfin 5xx processor family.


The gdb  simulator is really well defined and it helps me a lot to understand how processor works and what is the exact functionality of each instruction.


Currently, The functional simulator  that I  am developing  is almost  done. Just some interrupt supports are remained. The simulator can pass more than 85% of test benches that are provided in the testsuit of toolchain.


The developed simulator has the ability to support most architecturally visible part of Blackfin like hardware loop, parallel issuing of instructions and parallel MAC instructions. The good thing is that this simulator is based on SystemC and TLM libraries and has the ability of being cycle-accurate.


I have some questions regarding the micro-architecture details of processor. And I  appreciate a lot if you have a response for me, or can send me some related  documents/mails/post . Thanks a lot in advance for your attention.


1- What is the implication of the reserved registers in the Core Register Encoding Map.?Why the reserved registers  are part of the Core Register Encoding Map. It seems that these registers are addressable for some specific purposes and instructions. And if not, what are their implications. They are just regular micro-architecture registers or they have some specific purposes.?



2- What are the reserved bits in the in ASTATREG  ?



3- In  the gdb simulator uses store buffer to handle data dependencies in parallel issuing and parallel MAC and multiply instructions. My question is how you handle this issue in real processor. You have something like store buffer in micro-architecture, or you use just simple latch to delay the commitment of instructions.










2011-02-27 18:12:23     Re: Micro-Architecture Information

Mike Frysinger (UNITED STATES)

Message: 98454   


the core register map used in the toolchain reflects the hardware (the group and register encoding).  there are some registers that are simply not implemented in hardware and any attempts to use them will trigger a hardware error.  look at the opcode encoding in the Blackfin PRM for the register move instruction to see how these things are used.


the reserved ASTAT bits are not used by the hardware.  you can read/write/etc... them, but it doesnt matter.  they arent implicitly set/read anywhere by any insn like the defined status bits.


the Blackfin PRM talks about the dual mac/dag architecture.  the inputs are all latched at the same time, and it works because there are parallel execution units.