2010-12-17 13:24:35     Parallel instruction issue in bfin-sim

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2010-12-17 13:24:35     Parallel instruction issue in bfin-sim

Hamed Tabkhi (UNITED STATES)

Message: 96847   

 

Hello,

 

My name is Hamed Tabkhi. I am PhD student at northeastern university and working under supervision of Prof. G. Schirner. Currently, We are trying to develop an ISS (Instruction Set Simulator) for the Blackfin 527 processor core. our goal is improving cycle accuracy by capturing some micro-architectural detail. I saw bfin-sim, it is really well-defined. bfin-sim is a functional or in a better word instruction-accurate simulator and it does not support the micro-architecture details. In case of parallel issue instructions (64 bit instructions), bfin-sim detect 64 instructions by  "if ((iw0 & BIT_MULTI_INS) && (iw0 & 0xe800) != 0xe800" statement,  however, still I could not understand how bfin-sim decodes and executes 64 bit instructions ( which includes one 32 bit and two 16 bit instructions). I will appreciate a lot if you provide more information regarding the parallel execution in Blckfin, or what you did in bfin-sim.Thanks a lot for your attention.

 

I am looking forward to hearing from you.

 

 

 

Hamed

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2010-12-17 15:30:26     Re: Parallel instruction issue in bfin-sim

Mike Frysinger (UNITED STATES)

Message: 96848   

 

since a 64bit insn is really just standard 16bit/32bit insns with a special marker, we use the normal decode logic to handle it.

 

so if you look at interp_insn_bfin, the first call to _interp_insn_bfin returns the insn len.  with a 64bit insn, this will be 8.  we then decode the insns in the parallel slots right after with two more calls to _interp_insn_bfin.

 

also pay attention to INSN_LEN.  you see that on the first call (when noticing the 64bit insn), we set this to 8.  but when decoding the parallel insns, we dont update this field.  so the rest of the sim can key off of this field to detect that it is actually a multi-issue insn and fail when attempting to execute insns which are not valid in the parallel slots.

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2010-12-20 14:21:20     Re: Parallel instruction issue in bfin-sim

Hamed Tabkhi (UNITED STATES)

Message: 96882   

 

Hello,

 

Thanks a lot for your quick response, as you mentioned the 64 bit instructions just is a composition of standard instructions with some limitations. bfin-sim detects 64 bits instructions by looking at the special marker  (BIT_MULTI_INS in iw0). The thing that I cannot understand is why bfin-sim still uses the same decoding algorithm that used for regular instructions. So, my question is what is the effects of special marker used for detecting 64 instructions.

 

Bests,

 

Hamed Tabkhi

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2010-12-20 14:34:47     Re: Parallel instruction issue in bfin-sim

Mike Frysinger (UNITED STATES)

Message: 96883   

 

the 64bit marker is a single bit in the first 32bit insn.  if you ignore that, the 3 insns are exactly the same as if the 64bit marker didnt exist in the first place.  which means you can decode them the same way.

 

a simple example:

MNOP || [P0++] = R3 || R3 = [I1++];

 

this is the byte stream:

03 c8 00 18 03 92 0b 9c

 

so if you clear the multi-insn bit (0x8 in the 2nd byte):

03 c0 00 18 03 92 0b 9c

 

we get:

MNOP;

[P0++] = R3;

R3 = [I1++];

 

you can see the same with a simple .s file:

.long 0x1800c803 /* has multi-insn bit set */

.long 0x9c0b9203

 

.long 0x1800c003 /* has multi-insn bit cleared */

.long 0x9c0b9203

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2010-12-20 15:32:59     Re: Parallel instruction issue in bfin-sim

Hamed Tabkhi (UNITED STATES)

Message: 96885   

 

Thanks a lot. I got it.

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