2010-06-03 05:19:56     BF561 Simple dual core example

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2010-06-03 05:19:56     BF561 Simple dual core example

David Brandt (DENMARK)

Message: 90103   

 

Hi,

 

 

 

I'm using gcc (bfin-elf-gcc version 4.1.2) to program the BF561 bare metal and I'm trying to get a minimal example using both cores to work.

 

 

 

My program consists of a single file containing the two main functions, which simply performs endless loops:

 

 

 

int main(void)

 

{

 

  while(1);

 

}

 

 

 

int coreb_main(void)

 

{

 

  while(1);

 

}

 

 

 

If I disassemble the LDR file it seems to locate the two start procedures at 0xFFA00000 for core A and 0xFF600000 for core B, which as I understand it is as it is supposed to be.

 

 

 

However when I run the program it crashes with an external adressing errror.

 

 

 

Any suggestions on what I'm missing out. Should there be some special configuration in a linkerscript in order to make this work?

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2010-06-03 13:10:46     Re: BF561 Simple dual core example

Mike Frysinger (UNITED STATES)

Message: 90110   

 

look in the toolchain examples

 

http://blackfin.uclinux.org/gf/project/toolchain/scmsvn/trunk/examples/standalone/bf561-ezkit/

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2010-06-04 05:10:12     Re: BF561 Simple dual core example

David Brandt (DENMARK)

Message: 90124   

 

Hi,

 

I tried the example you linked to. I did completely as described.

 

I converted the 'blink' binary to a ldr file using the command:

 

bfin-elf-ldr -T bf561 -c blink.ldr blink

 

When I downloaded it and started it using u-boot I got the followin error message:

 

Ack! Something bad happened to the Blackfin!

 

SEQUENCER STATUS:

SEQSTAT: 0000c026  IPEND: 8030  SYSCFG: 0032

  HWERRCAUSE: 0x3: external memory addressing error

  EXCAUSE   : 0x26: dcplb miss                   

  physical IVG15 asserted : <0x03fc06fc> { _evt_default + 0x0 }

RETE: <0x348a6892> { ___umulsi3_highpart + 0x308cf622 }     

RETN: <0x03f9f1f8> /* unknown address */                    

RETX: <0x03fc0f2e> { _memcpy_ASM + 0x2e }                   

RETS: <0x03fc189e> { _memcpy + 0xca }                       

RETI: <0x03fc189e> { _memcpy + 0xca }                       

DCPLB_FAULT_ADDR: <0xff400000> { ___umulsi3_highpart + 0xfb428d90 }

ICPLB_FAULT_ADDR: <0x03fc0f2e> { _memcpy_ASM + 0x2e }            

 

PROCESSOR STATE:

R0 : 01000110    R1 : 01000110    R2 : 00000008    R3 : 00000000

R4 : 03f9f228    R5 : 03f9f224    R6 : 01000110    R7 : ff400000

P0 : ff400008    P1 : 01000118    P2 : 00000008    P3 : 03f9ff80

P4 : 03f9f667    P5 : 03f9f22c    FP : 00000000    SP : 03f9f124

LB0: 03fc0f2e    LT0: 03fc0f2c    LC0: 00000000               

LB1: 03fcfbdc    LT1: 03fcfbda    LC1: 00000000               

B0 : 307f7f99    L0 : 00000000    M0 : 045eda7a    I0 : 03fb0008

B1 : c4ce7a3b    L1 : 00000000    M1 : 2c665ad9    I1 : 03f9ff80

B2 : 366e7f51    L2 : 00000000    M2 : 112b5f22    I2 : 509f5856

B3 : b52dffdf    L3 : 00000000    M3 : 146f231f    I3 : 913c5d76

A0.w: 00000093   A0.x: 00000000   A1.w: 00000093   A1.x: 00000000

USP : 220e5c73  ASTAT: 02000021                                

 

Hardware Trace:

   0 Target : <0x03fc0cb0> { _bfin_panic + 0x0 }

     Source : <0x03fc075c> { _evt_default + 0x60 }

   1 Target : <0x03fc06fc> { _evt_default + 0x0 }

     Source : <0x03fc0f30> { _memcpy_ASM + 0x30 }

   2 Target : <0x03fc0f2e> { _memcpy_ASM + 0x2e }

     Source : <0x03fc0614> { _trap + 0x114 }    

   3 Target : <0x03fc05b8> { _trap + 0xb8 }     

     Source : <0x03fc0574> { _trap + 0x74 }     

   4 Target : <0x03fc0570> { _trap + 0x70 }     

     Source : <0x03fc0ed6> { _trap_c + 0x1e6 }  

   5 Target : <0x03fc0ece> { _trap_c + 0x1de }  

     Source : <0x03fc0e8e> { _trap_c + 0x19e }  

   6 Target : <0x03fc0d3a> { _trap_c + 0x4a }   

     Source : <0x03fc0d32> { _trap_c + 0x42 }   

   7 Target : <0x03fc0d2e> { _trap_c + 0x3e }   

     Source : <0x03fc0d26> { _trap_c + 0x36 }   

   8 Target : <0x03fc0d14> { _trap_c + 0x24 }   

     Source : <0x03fc0d04> { _trap_c + 0x14 }   

   9 Target : <0x03fc0cf0> { _trap_c + 0x0 }    

     Source : <0x03fc056c> { _trap + 0x6c }     

  10 Target : <0x03fc0500> { _trap + 0x0 }      

     Source : <0x03fc0614> { _trap + 0x114 }    

  11 Target : <0x03fc05b8> { _trap + 0xb8 }     

     Source : <0x03fc0574> { _trap + 0x74 }     

  12 Target : <0x03fc0570> { _trap + 0x70 }     

     Source : <0x03fc0ed6> { _trap_c + 0x1e6 }  

  13 Target : <0x03fc0ece> { _trap_c + 0x1de }  

     Source : <0x03fc0d2a> { _trap_c + 0x3a }   

  14 Target : <0x03fc0d28> { _trap_c + 0x38 }   

     Source : <0x03fc0d22> { _trap_c + 0x32 }   

  15 Target : <0x03fc0d14> { _trap_c + 0x24 }   

     Source : <0x03fc0d04> { _trap_c + 0x14 }   

 

### ERROR ### Please RESET the board ###

 

 

 

 

Any suggestions on how to solve this?

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2010-06-04 13:11:06     Re: BF561 Simple dual core example

Mike Frysinger (UNITED STATES)

Message: 90134   

 

u-boot probably doesnt support loading into coreb.  burn it into flash and let the bootrom do it.

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2010-06-04 13:44:18     Re: BF561 Simple dual core example

Mike Frysinger (UNITED STATES)

Message: 90138    alternatively, change the memcpy() in common/cmd_bootldr.c to dma_memcpy()

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2010-06-04 16:43:01     Re: BF561 Simple dual core example

Mike Frysinger (UNITED STATES)

Message: 90140   

 

ive committed a fix to svn trunk for this issue

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2010-06-18 05:28:04     Re: BF561 Simple dual core example

David Brandt (DENMARK)

Message: 90410   

 

Thanks for the help.

 

Upgrading U-boot solved the problem.

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