[#7137] change CONFIG_VCO_MULT values for uboot fails to make built uboot work

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[#7137] change CONFIG_VCO_MULT values for uboot fails to make built uboot work

Submitted By: Mingquan Pan

Open Date

2012-06-01 04:38:59     Close Date

2012-06-06 22:28:02

Priority:

Medium     Assignee:

Bob Liu

Category:

N/A     Fixed In Release:

N/A

Found In Release:

N/A     Status:

Closed

Board:

N/A     Processor:

BF609

Silicon Revision:

    Resolution:

Fixed

Is the bug repeatable?:

N/A     

Summary: change CONFIG_VCO_MULT values for uboot fails to make built uboot work

Details:

 

change CONFIG_VCO_MULT values for uboot fails to make built uboot work.

 

changes like:

 

diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h

index 899fcaf..60015a0 100644

--- a/include/configs/bf609-ezkit.h

+++ b/include/configs/bf609-ezkit.h

@@ -40,20 +40,20 @@

 

/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL             */

/* Values can range from 0-127 (where 0 means 128)                     */

-#define CONFIG_VCO_MULT                        (20)

+#define CONFIG_VCO_MULT                   16

 

/* CCLK_DIV controls the core clock divider                            */

/* Values can range from 0-31 (where 0 means 32)                       */

-#define CONFIG_CCLK_DIV                        (1)

+#define CONFIG_CCLK_DIV                   1

/* SCLK_DIV controls the system clock divider                          */

/* Values can range from 0-31 (where 0 means 32)                       */

-#define CONFIG_SCLK_DIV                        (5)

+#define CONFIG_SCLK_DIV                   4

/* Values can range from 0-7 (where 0 means 8)                         */

#define CONFIG_SCLK0_DIV               (1)

#define CONFIG_SCLK1_DIV               (1)

/* DCLK_DIV controls the DDR clock divider                             */

/* Values can range from 0-31 (where 0 means 32)                       */

-#define CONFIG_DCLK_DIV                        (2)

+#define CONFIG_DCLK_DIV                   2

/* OCLK_DIV controls the output clock divider                          */

/* Values can range from 0-127 (where 0 means 128)                     */

#define CONFIG_OCLK_DIV                        (16)

@@ -205,4 +205,5 @@

  * Pull in common ADI header for remaining command/environment setup

  */

#include <configs/bfin_adi_common.h>

+#undef CONFIG_CMD_KGDB

#endif

 

Built kernel fails to be reset.

 

the last work version is of May 28.

 

Follow-ups

 

--- Bob Liu                                                  2012-06-06 04:21:37

fixed, using div value instead of reading from register.

 

--- Mingquan Pan                                             2012-06-06 23:27:21

Yes, uboot now can start up at this freqs.

U-Boot 2011.09-dirty (ADI-2012R1) (Jun 07 2012 - 01:41:16), Build:

jenkins-label=UBOOT_BF609-EZKIT-158^M

^M

CPU:   ADSP bf609-0.0 (Detected Rev: 0.0) (parallel flash boot)^M

Board: ADI BF609 EZ-Kit board^M

       Support: http://blackfin.uclinux.org/^M

Clock: VCO: 25 MHz, Core: 400 MHz, System0: 100 MHz, System1: 100 MHz, Dclk:

200 MHz^M

RAM:   128 MiB^M

Flash: 16 MiB^M

MMC:   Blackfin SDH: 0^M

In:    serial^M

Out:   serial^M

Err:   serial^M

other init^M

Net:   mii0^M

Hit any key to stop autobo

*****************************

 

So close.

 

 

 

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