[#6544] dp83848 phy not detected on newer(?) version of ADSP-BF518F EZ-BOARD

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[#6544] dp83848 phy not detected on newer(?) version of ADSP-BF518F EZ-BOARD

Submitted By: Patrik Kluba

Open Date

2011-04-13 11:11:27     Close Date

2011-04-29 23:33:07

Priority:

Medium     Assignee:

Mike Frysinger

Category:

networking     Fixed In Release:

N/A

Found In Release:

2011R1     Status:

Closed

Board:

Ezbrd     Processor:

BF518

Silicon Revision:

0.2     Resolution:

Not reproducible

Is the bug repeatable?:

yes     

Summary: dp83848 phy not detected on newer(?) version of ADSP-BF518F EZ-BOARD

Details:

 

Tried with the trunk version of u-boot (926b78f73a84070e9f64f58d0831675dd391a2b4)

 

The newer(?) version of the bf-518f ezbrd has a National DP83848 PHY instead of the KSZ8993M switch. It has no fancy interfaces like SPI or I2C just the MDIO link. The PHY address is hardwired to 0x01 (and I've set CONFIG_PHY_ADDR to that). The correct schematics can be found here, just in case:

http://www.analog.com/static/imported-files/eval_kit_manuals/ADSP-BF518F%20EZ-Board%20Manual,%20Rev%201_1%20June%202009.pdf

 

CPU:   ADSP bf518-0.2 (Detected Rev: 0.2) (spi flash boot)

Board: ADI BF518F EZ-Board board

       Support: http://blackfin.uclinux.org/

Clock: VCO: 300 MHz, Core: 300 MHz, System: 75 MHz

RAM:   64 MiB

Flash: 4 MiB

MMC:   Blackfin SDH: 0

In:    serial

Out:   serial

Err:   serial

KGDB:  [on serial] ready

Net:   miiphy_register: added 'bfin_mac', read=0x03f91a60, write=0x03f91aa0

 

Output of 'mii info' with MII debugging enabled:

 

MII_PHYSID2 @ 0x0 = 0x0000

PHY_PHYIDR[1,2] @ 0x0 = 0x00000000

PHY 0x00: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x1 = 0x0000

PHY_PHYIDR[1,2] @ 0x1 = 0x00000000

PHY 0x01: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x2 = 0x0000

PHY_PHYIDR[1,2] @ 0x2 = 0x00000000

PHY 0x02: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x3 = 0x0000

PHY_PHYIDR[1,2] @ 0x3 = 0x00000000

PHY 0x03: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x4 = 0x0000

PHY_PHYIDR[1,2] @ 0x4 = 0x00000000

PHY 0x04: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x5 = 0x0000

PHY_PHYIDR[1,2] @ 0x5 = 0x00000000

PHY 0x05: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x6 = 0x0000

PHY_PHYIDR[1,2] @ 0x6 = 0x00000000

PHY 0x06: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x7 = 0x0000

PHY_PHYIDR[1,2] @ 0x7 = 0x00000000

PHY 0x07: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x8 = 0x0000

PHY_PHYIDR[1,2] @ 0x8 = 0x00000000

PHY 0x08: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x9 = 0x0000

PHY_PHYIDR[1,2] @ 0x9 = 0x00000000

PHY 0x09: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0xa = 0x0000

PHY_PHYIDR[1,2] @ 0xa = 0x00000000

PHY 0x0A: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0xb = 0x0000

PHY_PHYIDR[1,2] @ 0xb = 0x00000000

PHY 0x0B: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0xc = 0x0000

PHY_PHYIDR[1,2] @ 0xc = 0x00000000

PHY 0x0C: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0xd = 0x0000

PHY_PHYIDR[1,2] @ 0xd = 0x00000000

PHY 0x0D: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0xe = 0x0000

PHY_PHYIDR[1,2] @ 0xe = 0x00000000

PHY 0x0E: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0xf = 0x0000

PHY_PHYIDR[1,2] @ 0xf = 0x00000000

PHY 0x0F: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x10 = 0x0000

PHY_PHYIDR[1,2] @ 0x10 = 0x00000000

PHY 0x10: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x11 = 0x0000

PHY_PHYIDR[1,2] @ 0x11 = 0x00000000

PHY 0x11: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x12 = 0x0000

PHY_PHYIDR[1,2] @ 0x12 = 0x00000000

PHY 0x12: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x13 = 0x0000

PHY_PHYIDR[1,2] @ 0x13 = 0x00000000

PHY 0x13: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x14 = 0x0000

PHY_PHYIDR[1,2] @ 0x14 = 0x00000000

PHY 0x14: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x15 = 0x0000

PHY_PHYIDR[1,2] @ 0x15 = 0x00000000

PHY 0x15: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x16 = 0x0000

PHY_PHYIDR[1,2] @ 0x16 = 0x00000000

PHY 0x16: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x17 = 0x0000

PHY_PHYIDR[1,2] @ 0x17 = 0x00000000

PHY 0x17: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x18 = 0x0000

PHY_PHYIDR[1,2] @ 0x18 = 0x00000000

PHY 0x18: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x19 = 0x0000

PHY_PHYIDR[1,2] @ 0x19 = 0x00000000

PHY 0x19: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x1a = 0x0000

PHY_PHYIDR[1,2] @ 0x1a = 0x00000000

PHY 0x1A: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x1b = 0x0000

PHY_PHYIDR[1,2] @ 0x1b = 0x00000000

PHY 0x1B: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x1c = 0x0000

PHY_PHYIDR[1,2] @ 0x1c = 0x00000000

PHY 0x1C: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x1d = 0x0000

PHY_PHYIDR[1,2] @ 0x1d = 0x00000000

PHY 0x1D: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x1e = 0x0000

PHY_PHYIDR[1,2] @ 0x1e = 0x00000000

PHY 0x1E: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

MII_PHYSID2 @ 0x1f = 0x0000

PHY_PHYIDR[1,2] @ 0x1f = 0x00000000

PHY 0x1F: OUI = 0x0000, Model = 0x00, Rev = 0x00,  10baseT, HDX

 

Follow-ups

 

--- Mike Frysinger                                           2011-04-13 20:17:05

what is your output supposed to be showing ?  even the 2010R1 release of u-boot

supported the newer bf518f-ezbrds that dont have the switch on them.  and latest

trunk works fine for me:

 

U-Boot 2011.03-00073-g2be6b29 (ADI-2011R1-pre) (Apr 13 2011 - 20:05:49)

 

CPU:   ADSP bf518-0.0 (Detected Rev: 0.1) (parallel flash boot)

Board: ADI BF518F EZ-Board board

       Support: http://blackfin.uclinux.org/

Clock: VCO: 400 MHz, Core: 400 MHz, System: 80 MHz

RAM:   64 MiB

Flash: 4 MiB

MMC:   Blackfin SDH: 0

In:    serial

Out:   serial

Err:   serial

KGDB:  [on serial] ready

Net:   bfin_mac

Hit any key to stop autoboot:  0

bfin> mii info

PHY 0x01: OUI = 0x80017, Model = 0x09, Rev = 0x00, 100baseT, FDX

bfin> t 0 u-boot.bin

Using bfin_mac device

TFTP from server 192.168.1.2; our IP address is 192.168.1.15

Filename 'u-boot.bin'.

Load address: 0x0

Loading: #############

done

Bytes transferred = 182468 (2c8c4 hex)

 

--- Patrik Kluba                                             2011-04-14 04:05:51

the PHY is only detected after executing a dumb tftp command, like 'tftp 0.0.0.0

foobar' and stopping it with CTRL+C

 

MII_PHYSID2 @ 0x0 = 0xffff

MII_PHYSID2 @ 0x1 = 0x5c90

PHY_PHYIDR[1,2] @ 0x1 = 0x20005c90

PHY 0x01: OUI = 0x80017, Model = 0x09, Rev = 0x00, 100baseT, FDX

MII_PHYSID2 @ 0x2 = 0xffff

...

 

--- Mike Frysinger                                           2011-04-14 13:21:36

that's how the network is supposed to work in u-boot.  the phy is only ever

talked to when you attempt to use the network.  it should not (and is not)

initialized when simply booting and not using any network commands.

 

--- Mike Frysinger                                           2011-04-14 13:54:31

for posterity sake, ive also tested with a 1.0 board and things work fine.  the

previous test was with the national phy, but not the latest board rev.

 

the u-boot code is designed to support every board rev thus far in a single

binary.  so you're going to have to explain in detail what the actual problem is

that you're seeing.  is the network not working for you ?

 

the 2010R1 release:

 

U-Boot 2010.06 (ADI-2010R1-RC2) (Oct 20 2010 - 04:36:48)

 

CPU:   ADSP bf518-0.0 (Detected Rev: 0.2) (parallel flash boot)

Board: ADI BF518F EZ-Board board

       Support: http://blackfin.uclinux.org/

Clock: VCO: 400 MHz, Core: 400 MHz, System: 80 MHz

RAM:   64 MiB

Flash: 4 MiB

MMC:  Blackfin SDH: 0

In:    serial

Out:   serial

Err:   serial

KGDB:  [on serial] ready

Warning: Generating 'random' MAC address

Net:   bfin_mac

Hit any key to stop autoboot:  0

bfin> t 0 u-boot.ldr

Using bfin_mac device

TFTP from server 192.168.0.2; our IP address is 192.168.0.15

Filename 'u-boot.ldr'.

Load address: 0x0

Loading: ##############

done

Bytes transferred = 191148 (2eaac hex)

bfin>

 

current trunk (default):

 

U-Boot 2011.03-00000-g6d7e35b (ADI-2011R1-pre) (Apr 14 2011 - 13:30:32)

 

CPU:   ADSP bf518-0.0 (Detected Rev: 0.2) (parallel flash boot)

Board: ADI BF518F EZ-Board board

       Support: http://blackfin.uclinux.org/

Clock: VCO: 400 MHz, Core: 400 MHz, System: 80 MHz

RAM:   64 MiB

Flash: 4 MiB

MMC:   Blackfin SDH: 0

In:    serial

Out:   serial

Err:   serial

KGDB:  [on serial] ready

Net:   bfin_mac

Hit any key to stop autoboot:  0

bfin> t 0 u-boot.ldr

Using bfin_mac device

TFTP from server 192.168.0.2; our IP address is 192.168.0.15

Filename 'u-boot.ldr'.

Load address: 0x0

Loading: ##############

done

Bytes transferred = 204700 (31f9c hex)

bfin>

 

current trunk (built for bf518-0.2):

 

U-Boot 2011.03-00000-g6d7e35b-dirty (ADI-2011R1-pre) (Apr 14 2011 - 13:33:36)

 

CPU:   ADSP bf518-0.2 (Detected Rev: 0.2) (parallel flash boot)

Board: ADI BF518F EZ-Board board

       Support: http://blackfin.uclinux.org/

Clock: VCO: 400 MHz, Core: 400 MHz, System: 80 MHz

RAM:   64 MiB

Flash: 4 MiB

MMC:   Blackfin SDH: 0

In:    serial

Out:   serial

Err:   serial

KGDB:  [on serial] ready

Net:   bfin_mac

Hit any key to stop autoboot:  0

bfin> t 0 u-boot.ldr

Using bfin_mac device

TFTP from server 192.168.0.2; our IP address is 192.168.0.15

Filename 'u-boot.ldr'.

Load address: 0x0

Loading: ##############

done

Bytes transferred = 204332 (31e2c hex)

bfin>

 

--- Mike Frysinger                                           2011-04-29 23:33:07

please re-open if you can describe actual issues that you're having

 

 

 

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