[#6285] MMC/SD can't work on bf537-stamp when either icache or dcache is off
Submitted By: Vivi Li
N/A Fixed In Release:
Found In Release:
Assigned (Not Start)
Is the bug repeatable?:
Summary: MMC/SD can't work on bf537-stamp when either icache or dcache is off
MMC/SD can't work on bf537-stamp when either icache or dcache is off. This happens on both branch 2010r1 and trunk.
Last passed version is 2405; first failed version is 2411.
Bellow is the log:
U-Boot 2010.06-svn2467 (ADI-2010R1) (Oct 09 2010 - 14:29:38)
CPU: ADSP bf537-0.2 (Detected Rev: 0.2) (bypass boot)
Board: ADI BF537 stamp board
Clock: VCO: 400 MHz, Core: 200 MHz, System: 100 MHz
RAM: 64 MiB
Flash: 4 MiB
KGDB: [on serial] ready
Hit any key to stop autoboot: 0
bfin> icache on
Instruction Cache is ON
bfin> dcache off
Data (writethrough) Cache is OFF
bfin> set mmc_cs 4; set mmc_hz 20000000
bfin> printenv mmc_cs mmc_hz
bfin> mmc init
using spi0.4 at 20000000 hz with mode 3
mmc1 is available
bfin> fatls mmc 0
** Unable to use mmc 0:1 for fatls **
--- Sonic Zhang 2010-10-12 06:10:55
This bug was introduced by your latest change to the SPI DMA code before code
freeze. Could you take a look?
--- Mike Frysinger 2010-10-12 21:10:14
i'm not worried about cache off behavior. does the issue only crop up when
caches are off ?
--- Vivi Li 2010-10-13 23:52:32
Yes, it happens only when either one of the caches is off.
--- Sonic Zhang 2010-10-18 22:32:47
I guess the conclusion is that we should not worry about spi device with cache
off? If so, Vivi may disable SPI cases with cache off.
--- Mike Frysinger 2011-05-07 18:09:57
i dont think any customer will ever run with caches turned off since the speed
loss is so high. it is useful to test with caches off as the increased latency
sometimes can detect race conditions in the code.
does this still fail with the newer mmc/spi driver ? i think this test was run
against the old one which no longer exists ...
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