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Plotting JFET source follower input capacitance in the function of frequency

Thread Summary

The user seeks to plot the input capacitance and resistance of a JFET source follower circuit (2N4416) over a frequency range of 1 MHz to 10 MHz. The final answer provides a method to calculate the input capacitance using the formula Ig(J1)/(V(ugs)*2*3.1454*frequency), resulting in 16.2 pF at 1 MHz. However, the user notes that this value seems high compared to the datasheet, which specifies Cgs as 2.41 pF and Cgd as 1.6 pF.
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Category: Software
Software Version: LTspice (x64): 26.0.2

Hi,

I would like to plot the input capacitance (and the input resistance) of a jfet source follower circuit in the function of frequency .   The input impedance is complex of course in the frequency range involved between 1 MHz and 10 MHz but I need help in doing this. 

I used the 2N4416 jfet model and its input capacitance is known from data sheet (which is about 3-4 pF) but I wish to see it plotted on the vertical axis while the horizontal axis shows the frequency range. 

Here is the schematic I use for simulation, together with the small signal AC simulation plot on the voltage output and I attached the asc circuit file too

JFET source follower tests 1.asc

Thanks for any help in advance. 

Gyula

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  • Hi mtwieghr,

    I understand,  thank you. I thought there should be explanation why I did not find increase in Cin. 

    Just for your information:  Here is a link to the 2N4416  which includes Ciss, Coss and the reverse Crss capacitances, all for common source config, at Vgs=0V. 

    And the built-in Spice model includes these capacitance values only:  Cgd=1.6pF and  Cgs=2.414pF  so these are considered in the simulation.  So Ciss in the model is the sum of these, i.e. 4.014 pF but then this is valid at Vgs=0 V, I understand. 

    Now I would like to return to plotting the input resistance in the function of frequency in this same circuit.  Earlier I wrote this post and included a formula Rin = 1/Re(Ig(J1)/V(ugs))   (and a plot file) for the input resistance but later I realized that if I vary the 10 MegOhm gate resistance, the plot does not change, so the formula is wrong. 

     I cannot figure out how to change or devise a formula for plotting Rin correctly. 

    Would you mind checking this, when you have time, I would appreciate it.  

    Thanks,

    Gyula 

Reply
  • Hi mtwieghr,

    I understand,  thank you. I thought there should be explanation why I did not find increase in Cin. 

    Just for your information:  Here is a link to the 2N4416  which includes Ciss, Coss and the reverse Crss capacitances, all for common source config, at Vgs=0V. 

    And the built-in Spice model includes these capacitance values only:  Cgd=1.6pF and  Cgs=2.414pF  so these are considered in the simulation.  So Ciss in the model is the sum of these, i.e. 4.014 pF but then this is valid at Vgs=0 V, I understand. 

    Now I would like to return to plotting the input resistance in the function of frequency in this same circuit.  Earlier I wrote this post and included a formula Rin = 1/Re(Ig(J1)/V(ugs))   (and a plot file) for the input resistance but later I realized that if I vary the 10 MegOhm gate resistance, the plot does not change, so the formula is wrong. 

     I cannot figure out how to change or devise a formula for plotting Rin correctly. 

    Would you mind checking this, when you have time, I would appreciate it.  

    Thanks,

    Gyula 

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