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Recently, while studying Christophe Basso's Simplis loop control design and simulating Boost VM mode control, I tried to reproduce the results using LTspice. However, with exactly the same parameters, the phase margin was 20 degrees lower. Why is this happening?
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Some comments and observations:
The LT1720 is a 3.3 V / 5 V comparator with a supply voltage rating up to 12 V.
The comparator output cannot provide enough current to drive the MOSFET as effectively as a dedicated gate driver. As a result, additional switching delay may be introduced.
The peak-to-peak amplitude of the FRA signal seems quite large. Are the results similar when using a lower amplitude?
The diode model is not defined.
Christophe basso speaks about the difference between both regulation mode.
We do not know which values were calculated by SIMPLIS, making it difficult to verify all the component parameters and simulation assumptions.
