DFF Model Does Not Work As Expected

Question

Hello ADI, 
 I have been working on a design for a circuit and I discovered that the DFF model does not work properly. Specifically, if you preset the FF Q=1 with D=GND, and then toggle the CLK, the 0 on D does not ever propagate to Q. All you have to do is build this circuit. Tests shown below (see the preset & 0 Propagation Test). For the FF vhigh=5 vlow=0 ref=2V td=15ns. 
 Thanks, 
 Phil

mtwieghr · Accepted Answer

I believe what you're describing is normal behavior. The dflop is one of the "A" special functions, like the other basic logic gate models. When any pin is connected directly to global GND, that pin's function is ignored entirely, as if it weren't even there. For example, grounding the inputs of an AND gate won't force the gate's output low. If you want to apply a static logic low to the D pin, don't connect it directly to global GND. 
 edit: To be precise, pins are ignored if they are tied to the same net as their pin 8. In most cases (including the OP's schematic), pin 8 is connected to global GND, in which case my above comment is correct.)

hrail · Answer

Some texts in the help file-->circuit elements-->A. Special Functions: 
 Unused inputs and outputs are to be connected to terminal 8. LTspice recognizes that as a flag that that terminal is not used and removes it from the simulation. This leads to the potentially confusing situation where AND gates act differently when an input is grounded or at zero volts. If ground is the gate's common, then the grounded input is not at a logic false condition, but simply not part of the simulation. The reason that these gates are implemented like that is that this allows one device to act as 2-, 3-, 4- or 5- input gates with true, inverted, or complementary output with no simulation speed penalty for unused terminals. 
 Maybe have some information

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DFF Model Does Not Work As Expected

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