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DFF Model Does Not Work As Expected

		
	
				

			

									
					    Mtr90
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Aug 30, 2026 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user encountered an issue with the DFF model where a preset Q=1 with D=GND prevented 0 from propagating to Q on clock toggles. The final answer clarifies that connecting any pin directly to global GND ignores the pin's function. A workaround is to tie the D input to a 0V source or ground through a resistor to ensure proper 0 propagation at the positive clock edge.
                        	    

                
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Category: Software

    		        		            		    
Product Number:  LTSPICE 26 Bug, LTSPICE  

    		        		        		        
Software Version: LTSPICE 24 and later

    		    		    

		    		    
		    			

			    
Hello ADI,


I have been working on a design for a circuit and I discovered that the DFF model does not work properly.  Specifically, if you preset the FF Q=1 with D=GND, and then toggle the CLK, the 0 on D does not ever propagate to Q.  All you have to do is build this circuit.  Tests shown below (see the preset & 0 Propagation Test).  For the FF vhigh=5 vlow=0 ref=2V td=15ns.  


Thanks,


Phil  




 

			

			
									
		                             
                        

    

                                            
                 software
                
                                                    
                 LTspice
                
                                                    
                 LTSPICE 24 and later
                
                                                    
                 LTSPICE 26 Bug
                
                                
            

    
    
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			


				
	









	
    
	

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                on Aug 30, 2026 9:58 PM
            
            
						
			            		
    
		
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    Update:  For the preset and  0 propagate test, after further testing, if the DFF D input is tied to a 0V source OR to ground through a resistor, the 0 will propagate at the pos clk edge.  If D is simply tied to ground, the 0 will not propagate as it would in a real circuit.
    

    

    Phil
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Aug 31, 2026 11:02 AM
            
            
						
			            		
    
		
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    I believe what you're describing is normal behavior. The dflop is one of the "A" special functions, like the other basic logic gate models. When any pin is connected directly to global GND, that pin's function is ignored entirely, as if it weren't even there. For example, grounding the inputs of an AND gate won't force the gate's output low. If you want to apply a static logic low to the D pin, don't connect it directly to global GND.
    

    edit: To be precise, pins are ignored if they are tied to the same net as their pin 8. In most cases (including the OP's schematic), pin 8 is connected to global GND, in which case my above comment is correct.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Aug 31, 2026 8:43 PM
            
            
												
						in reply to mtwieghr
					
										
			            		
    
		
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    I see so, for all special logic functions, the pins can be grounded through another component to get a 0.  Direct ground forces the pin to be ignored.  What is the effect if a pin is tied to VCC?  Where is this documented?  Thank you for the help, I was not aware of this effect. 
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Aug 31, 2026 10:24 PM
            
            
						
			            		
    
		
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    Some texts in the help file-->circuit elements-->A. Special Functions:
    

    Unused inputs and outputs are to be connected to terminal 8. LTspice recognizes that as a flag that that terminal is not used and removes it from the simulation. This leads to the potentially confusing situation where AND gates act differently when an input is grounded or at zero volts. If ground is the gate's common, then the grounded input is not at a logic false condition, but simply not part of the simulation. The reason that these gates are implemented like that is that this allows one device to act as 2-, 3-, 4- or 5- input gates with true, inverted, or complementary output with no simulation speed penalty for unused terminals.
    

    Maybe have some information
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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                on Sep 1, 2026 9:46 AM
            
            
												
						in reply to Mtr90
					
										
			            		
    
		
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    The special function components have no concept of "VCC". Any pins connected to the same net as their pin 8 will be ignored, regardless of the actual voltage on that net.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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