Hi everyone,
I am currently developing an LT8610-based buck converter and using LTspice for pre-compliance conducted EMI simulation. I am employing a symmetrical LISN setup and have integrated parasitic models (ESR/ESL) for the input capacitors (CinB, CinC) along with common-mode coupling paths (C_stray) to simulate the noise environment.
Current Methodology:
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Simulation: Transient analysis with a Hanning-windowed FFT.
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Analysis: I am using standard LISN matrix decomposition to isolate noise modes: $V_{DM} = V_1 - V_2$ and $V_{CM} = V_1 + V_2$.
Observation:
While my simulation successfully captures the fundamental switching harmonics, my total conducted emissions peak at approximately 45 dBµV. This is significantly lower than the 80–90 dBµV peaks typically seen in reference EMI profiles or LTpowerCAD predictions for similar topologies.
Questions:
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Measurement Point: Is this amplitude discrepancy primarily due to the fact that I am measuring at the filter output (attenuated), whereas reference charts often display source noise (unattenuated)?
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Parasitic Modeling: What is the industry-standard approach in LTspice to accurately model PCB trace inductance and loop area to align simulated "source" noise levels with reference design data?
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Switching Dynamics: Are there specific non-ideal switching models or parameters for the LT8610 internal MOSFETs that I should be incorporating to more accurately represent high-frequency common-mode energy contributions?
I would appreciate any guidance on how to bridge this delta between my simulated filter output and theoretical reference EMI profiles.
Best regards,
Varad
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