LTspice
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LTspice® is a powerful, fast, and free SPICE simulator software, schematic capture and waveform viewer with enhancements and models for improving the simulation...
LTspice on Analog.com
LT8610
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The LT8610 is a compact, high efficiency, high speed synchronous monolithic step-down switching regulator that consumes only 2.5μA of quiescent current...
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LT8610 on Analog.com


Hi everyone,
I am currently performing a pre-compliance conducted EMI simulation for an LT8610-based buck converter design in LTspice. I am modeling the input stage using a symmetrical LISN setup and have included parasitic models (ESR/ESL) for the input capacitors (CinB, CinC) and common-mode coupling paths (C_stray) to ground.
Current Setup:
Simulation: Transient analysis with Hanning window FFT.
Math: I am decomposing the noise into Differential Mode (V_DM = V1 - V2) and Common Mode (V_CM = V1 + V2) using the standard LISN matrix equations.
Observation: While I have successfully captured the fundamental switching harmonics, my simulation results for total conducted emissions peak at approximately 45 dBµV. In contrast, reference EMI profiles for this topology (like those in LTpowerCAD or typical ADI reference designs) show peak emissions closer to 80–90 dBµV in the same frequency range.
My Questions:
Is the amplitude delta I am seeing primarily due to the difference between the source noise (unattenuated) typically shown in reference charts versus the filter output (attenuated) I am measuring in my schematic?
What is the recommended approach in LTspice to model the PCB loop area/trace inductance more accurately to ensure the "source" noise levels match reference expectations?
Are there specific non-ideal models for the LT8610's internal MOSFET switching characteristics that I should be including to better account for high-frequency common-mode energy?
I appreciate any insights on bridging the gap between my current LTspice filter output and the theoretical reference EMI profiles.
Thanks, Varad