Net names are not recognized in the hierarchical designs plots

Hi again ElShang,

A few more FYI's -

In your picture, you show a net that has two Labels attached to it, +VSYS and TEST_NAME.  It is not a good idea to do that.  Every net or node in SPICE can have only one nodename.  By attaching two Labels, you are suggesting that it has two nodenames.  But that is impossible since it can have only one.  Fortunately, LTspice can usually figure it out.  It does that by arbitrarily choosing one of the two names and ignoring the other.  But it also remembers the other one you tried to use and it attempts to "alias" it back to the nodename that it chose.  However, there are situations where this fails.  In all cases, you should use only one nodename (one Label) attached to any net.

Also you wrote that "it is impossible to name so it is used in the plot."  I understand the frustration, but actually that is not quite true.  Any subcircuit net that reaches a wire in the top-level schematic gets (inherits) the nodename from the top-level schematic.  Therefore, its name in the top-level schematic is the one you should use and reference in waveform plots.

If there is confusion about finding what a subcircuit's nodename was changed to, LTspice makes it easy to avoid worrying about that.  When you have the top-level schematic and the waveform window open in LTspice, use your mouse and click on the hierarchical symbol to "move" into that subcircuit.  Now you can click on any of the wires in that lower-level schematic, and LTspice will plot it.  You don't need to know what its nodename happens to be.

If you are creating plots for publication and need them to show specific nodenames, just make sure that each node whose waveform you want to plot comes out on a "pin" and then connects to a top-level net with a name on it.  Those top-level nodenames are the ones you will see in the plots.

Andy

AndyI said:

This situation is inherent in all SPICE netlists that include subcircuits, and it is a situation that has been in SPICE for all time; it is not unique to LTspice.  But you might not understand why it is necessary.

Well, I thought about something like that. So that's basically a no-surprise at all.
Basically, the "subcircuits" is the same as "module" in the programming languages. Both have some local entities, which must be duplicated in this or other wat.

But thanks for the clarification anyway. :-) 

AndyI said:

In your picture, you show a net that has two Labels attached to it, +VSYS and TEST_NAME.  It is not a good idea to do that.

Oh yeah, I have already ran into this sort of issue. I mean the one when I have two name for the same net. But this was just an example to depict what I was trying to accomplish.

AndyI said:

If there is confusion about finding what a subcircuit's nodename was changed to, LTspice makes it easy to avoid worrying about that.  When you have the top-level schematic and the waveform window open in LTspice, use your mouse and click on the hierarchical symbol to "move" into that subcircuit.  Now you can click on any of the wires in that lower-level schematic, and LTspice will plot it.  You don't need to know what its nodename happens to be.

That's exactly how I peek and poke around the hierarchical design. Trying to manually find a point of interest using the V(n???) notion is like finding a needle in a haystack. Especially taking into account the node names "mangling" performed by the SPICE during netlist flattening.

AndyI said:

If you are creating plots for publication and need them to show specific nodenames, just make sure that each node whose waveform you want to plot comes out on a "pin" and then connects to a top-level net with a name on it. 

True, that's a nice alternative, your suggestion is appreciated. A little issue with it may "pollute" the schematic. 

Consider I have subcircuits A and B instantiated in the circuit "root". A and B represent distinct hardware modules and have a certain interface. This way I consider the top-level "ports" as the connectors of some sort, representing the way the modules A and B interact with each other. So creating additional ports to peek the internals makes circuitry a little "messy".

But that's the matter of taste, of course.

==========

All in all, it is clear that it is impossible to explicitly name a net in the hierarchical design using the standard SPICE facilities. But maybe in the future version, authors of LTspice will create an option to assign an "aliase" of the net/node exclusively on the plot tab. Something like this:

This way the underlying SPICE conventions remains uncompromised.

 ==========

Thanks for your time and good luck!

AndyI said:

This situation is inherent in all SPICE netlists that include subcircuits, and it is a situation that has been in SPICE for all time; it is not unique to LTspice.  But you might not understand why it is necessary.

Well, I thought about something like that. So that's basically a no-surprise at all.
Basically, the "subcircuits" is the same as "module" in the programming languages. Both have some local entities, which must be duplicated in this or other wat.

But thanks for the clarification anyway. :-) 

AndyI said:

In your picture, you show a net that has two Labels attached to it, +VSYS and TEST_NAME.  It is not a good idea to do that.

Oh yeah, I have already ran into this sort of issue. I mean the one when I have two name for the same net. But this was just an example to depict what I was trying to accomplish.

AndyI said:

If there is confusion about finding what a subcircuit's nodename was changed to, LTspice makes it easy to avoid worrying about that.  When you have the top-level schematic and the waveform window open in LTspice, use your mouse and click on the hierarchical symbol to "move" into that subcircuit.  Now you can click on any of the wires in that lower-level schematic, and LTspice will plot it.  You don't need to know what its nodename happens to be.

That's exactly how I peek and poke around the hierarchical design. Trying to manually find a point of interest using the V(n???) notion is like finding a needle in a haystack. Especially taking into account the node names "mangling" performed by the SPICE during netlist flattening.

AndyI said:

If you are creating plots for publication and need them to show specific nodenames, just make sure that each node whose waveform you want to plot comes out on a "pin" and then connects to a top-level net with a name on it. 

True, that's a nice alternative, your suggestion is appreciated. A little issue with it may "pollute" the schematic. 

Consider I have subcircuits A and B instantiated in the circuit "root". A and B represent distinct hardware modules and have a certain interface. This way I consider the top-level "ports" as the connectors of some sort, representing the way the modules A and B interact with each other. So creating additional ports to peek the internals makes circuitry a little "messy".

But that's the matter of taste, of course.

==========

All in all, it is clear that it is impossible to explicitly name a net in the hierarchical design using the standard SPICE facilities. But maybe in the future version, authors of LTspice will create an option to assign an "aliase" of the net/node exclusively on the plot tab. Something like this:

This way the underlying SPICE conventions remains uncompromised.

 ==========

Thanks for your time and good luck!