Net names are not recognized in the hierarchical designs plots

Question

Hello to the community! 
 It is not an issue but a feedback for the developer. Maybe they will take it into considerations in the future versions. Consider the following usecase. 
 I have a circuit named " power.asc ". And I'm testing/debugging it in a few higher-level files named " power_test_1.asc ", " power_test_2.asc " and so on. Each contains a specific scenario to evaluate. So I follow the " Hierarchy " chapter in the help and create the " power.asy " symbol containing the ports. 
 A little problem is now it is impossible to name so it is used in the plot. Just V(${NODE_NUMBER}). Here is the depiction: 
 
 The "+VSYS" name is plotted as simple V(n002). Neither the "+VSYS" nor "TEST_NAME" are recognized. 
 It is not a big deal for most people. But recently I was preparing the report, and it took me a bunch of time to create a readable legend for the traces using Paint. :-D 
 I believe that the root cause is hidden somewhere deep in the netlist processor, so it may be a little difficult to fix. So something like an "alias name" for the trace on the plot will be highly appreciated by the strugglers like myself. The node name remains the same, but it has the human-readable name. 
 
 Thanks for your attention.

AndyI · Accepted Answer

Hi ElShang, 
 This situation is inherent in all SPICE netlists that include subcircuits, and it is a situation that has been in SPICE for all time; it is not unique to LTspice. But you might not understand why it is necessary. 
 Consider that you made a subcircuit that has a nodename "1". Now consider that you use five instances of that subcircuit in your top-level circuit or netlist. Clearly, they can not keep the same nodename "1", because that would short-circuit all of them. 
 Also consider if you had only one instance of this subcircuit, but your top-level netlist also had a node named "1". If it kept both with the same nodename, they would be short-circuited together. 
 You would not want either of those to happen. 
 Therefore, SPICE alters the nodenames you had internal to your subcircuits, when it 'flattens' the netlist into one netlist. SPICE has always done that, and there is no way around it. 
 Whether you named your internal net "1" or "+VSYS" it makes no difference. They must be converted to new nodenames to avoid duplication, with consequent short-circuits. 
 In your case, I guess the node "+VSYS" was connected to a top-level node that did not have an explicit name (or Label) attached to it, and its nodename happened to be "N002". So that became the actual nodename of that net, both external to the subcircuit and inside it. They are the very same net, so they must have the same nodename. If you have nets that reach the top-level schematic, their nodenames in the top-level schematic will be used for the internal portions too, since they are the same. 
 Regards, 
 Andy)

SLA Status	Assignee	Support Status
SLA Closed. Met after 27 hours	MStokowski	Closed

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Net names are not recognized in the hierarchical designs plots

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