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LTspice bug translating PSpice syntax

Category: Software
Product Number: LTspice 24.1.10, LTspice
Software Version: 24.1.10

Hi, 

I believe I have found a bug in LTspice support for the PSpice VSWITCH model type. 

I am trying to use an unencrypted PSpice model for the UC3843 provided by TI at UCCx8C43 Unencrypted PSpice Transient Model. This model has a couple of items that must be modified for use with LTspice; there are a few "^" characters used for exponentiation, and V3 generates a warning because it is missing a value of 0. Even with those changes (and several other minor mods) I am having little success running a boost converter circuit using this controller. So I decided to start simulating some of the subcircuits on there own to see what worked and what didn't. 

One of the first function on the chip is the oscillator, described at the very beginning of the spice library file as ("..." added where lines were dropped):

.SUBCKT UCC28C43_STEADY  COMP   FB   CS   RTCT    GND    OUT   VDD   VREF  
****OSCILLATOR*****
STOF1 8 GND RTCT GND SOSC
GBDISCH RTCT GND Value = { IF ( V(8,GND) < 2.5 & V(13,GND) > 2.5, 8.4M, 0 ) }
RPULL 8 VREF 100K
...
****REFERENCE*******
EBREF 13 GND Value = { IF ( V(19,GND) > 6, 5, 0 ) } 
RREG 10 VREF 0.158
CREF VREF GND 1N
V3 13 10 
...
.MODEL SOSC VSWITCH (RON=.01 ROFF=1MEG VT=1.45 VH=0.95) ; VT=1.45 set to match 53k @ 3.3n/10k

I created a standalone model of the oscillator circuit as a separate LTspice schematic. This file uses the definition of the G source and the voltage controlled switch identical to those defined in the TI library file.

uc3843 osc.asc

This file runs at an extremely slow rate, simulating fs/s with many "Warning: Simulation tolerance relaxed to achieve convergence from..." messages generated and logged. The simulation never completes and has to be stopped manually.

To correct this I replaced the VSWITCH in the SOSC model definition with the LTspice equivalent SW. With this simple change the simulation runs to completion is a few seconds. The strange thing is the Expanded Netlist for both versions is exactly the same, showing SOSC defined as a SW model.

    --- Expanded Netlist ---
S1 0 CLK RTCT 0 SOSC 
V1 N001 0 DC=5
R2 VREF RTCT R=10000
R3 VREF N001 R=0.158
R1 VREF CLK R=100000
C1 RTCT 0 CAPACITANCE=3.3e-09
C2 VREF 0 CAPACITANCE=1e-09
GBDISCH RTCT 0 I=if((v(clk)<2.5)&(v(vref)>2.5),0.008400000000000001,0)
.model SOSC SW(RON=0.01 ROFF=1000000 VT=1.45 VH=0.95)

.end

The behavior of the circuit is very much different with the VSWITCH model type in the schematic even though both VSWITCH and SW produce the same Expanded Netlist. I believe this must be a bug.

Parents
  • Dear  ,

    This is a feature, not a bug.

    If you use "VSWITCH" instead of "SW", you invoke pspice compatibility. That means you have to specifiy the input thresholds with parameters "VON" and "VOFF", just like in pspice.

    Best Regards,
    Mathias

  • This is problematic because the published subcircuit uses VSWITCH along with the VT and VH parameters which does work in PSpice (possibly for LTspice compatibility). LTspice should accept the same syntax as PSpice. The fact PSpice accepts undocumented parameters is no different than the many undocumented parameters accepted by LTspice. As much as possible, you shouldn't require users to make edits to PSpice subcircuits that work in PSpice. 

    Furthermore, LTspice shows that it translated the PSpice VSWITCH into an LTspice SW in the Expanded Netlist. If it is making such a translation it should translate the threshold voltages as well. In this case they are already specified using the LTspice parameters, so no translation is required.

    Ultimately, we have two schematics which produce the same Expanded Netlist, but have very different behavior. This should not happen.

  • Hi  ,

    This is problematic because the published subcircuit uses VSWITCH along with the VT and VH parameters which does work in PSpice (possibly for LTspice compatibility). LTspice should accept the same syntax as PSpice.

    A bit circular, but yes, would be nice to have the complete set of all possible parameters be translated both ways: PSPICE <> LTspice. Unfortunately, to do so could possibly result in unintended behavior in other designs.

    LTspice's current netlist syntax requirements aim to improve determinism, and to enable future enhancements; with the additional goal of minimizing undocumented behaviors, which must be accounted for in updates (straight-up PSPICE support aside). A thought test: What if the params Vt, Vh, VON and VOFF are all specified? I imagine we would have to throw an error. How would you handle this case?

    Unfortunately, it opens quite a can of worms to support a circular definition of VSWITCH param that are not VSWITCH params in an effort to match how PSPICE supports a model that is actually ill-defined (by using LTspice SW params). Ironically, the model itself would work fine if it were limited to PSPICE's documented parameters.

    mike

  • Hi Mike,

    I fail to see how your concerns about unintended behavior could be a problem. Working designs use either SW or VSWITCH model types. If they currently use SW there will be no change in behavior. If they currently use VSWITCH and work they must be using the VON and VOFF parameters. If they currently use VSWITCH and the VT and VH parameters they don't work.

    Furthermore, LTspice currently shows it has converted the VSWITCH into a SW model in the Expanded Netlist, using the correct VT and VH parameters, but the circuit does not simulate correctly in LTspice.

    It seems clear to me that the correct values reported in the Expanded Netlist must not be the values actually used to run the simulation. This is the bug!

    This can be checked by changing only the model type from VSWITCH to SW. LTspice produces the EXACT SAME EXPANDED NETLIST in both cases, but only the circuit using SW simulates correctly.

    Have you tried to run the very simple sample circuit I uploaded? 

    I don't think it is likely to be a concern to have both sets of parameters defined, but for completeness, if they are both specified I would do like other cases of repeated parameters and use the last value(s) specified. If the last value is a Vt or Vh then use those values in the converted SW. If the last value is an VON or VOFF, use those values to calculate the equivalent Vt and Vh for the converted SW. If only one value is specified for the last set (say VON but no VOFF, or Vt but no Vh) then the default value should be used for the missing value in the set. 

    VSWITCH (VON=2 VOFF=1 Vt=2.5 Vh=0.5) => SW (Vt=2.5 Vh=0.5)
    VSWITCH (Vt=2.5 Vh=0.5 VON=2) => SW (Vt=1 Vh=1) since VOFF is missing default value of 0 was used.

    Currently in LTspice, if I put multiple mixed parameters on a SW model I get no indication of any error or warning, but I have no idea which parameters are used. Try this:

    V1 N001 0 1
    V2 N002 0 PWL(0 0 1 5 2 0)
    S1 0 N001 N002 0 ASW
    .model ASW SW (Ron=1 Roff=10 Vt=3 VON=2 VOFF=1 Vh=1)
    .tran 2
    

    Which expands to:

    V1 N001 0 DC=1
    S1 0 N001 N002 0 ASW 
    V2 N002 0 PWL=+0,0,+1,5,+1,0
    .model ASW SW(Ron=1 Roff=10 Vt=3 VON=2 VOFF=1 Vh=1)
    

    This seems to turn on at 2 V and off at 1 V, seeming to ignore Vt and Vh, and using VON and VOFF even though they are undocumented for a SW model.

    Again, ultimately LTspice says it is using the same netlist whether I use VSWITCH( Vt Vh) or SW (Vt Vh) as my input. In both cases it says it is using SW (Vt Vh) to simulate, but only one of those circuits simulates correctly. This is a bug in LTspice! 

  • Hi  ,

    Turns out the problem here is with the expanded netlist being somewhat vague in what happens in simulation. The expanded netlist will be updated to more clearly represent the simulation.

    mike

  • Why not simply document that SW and VSWITCH are both accepted as model types for a voltage controlled switch, and then document all four parameters (Vt, Vh, VON, and VOFF) that may be used with those models along with a clear explanation of how LTspice chooses the limits it actually uses in a simulation. 

    I see no reason why LTspice accepts one set of PSpice parameters and not the other. Both are accepted by PSpice, and LTspice accepts the VSWITCH model type for PSpice compatibility, so LTspice should also accept both sets of PSpice model parameters. Especially when it is simple to convert from one to the other. 

    The goal, after all, is to allow LTspice to run PSpice models without modification! If I have to modify the PSpice model to use it with LTspice, then LTspice isn't really PSpice compatible.

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  • Why not simply document that SW and VSWITCH are both accepted as model types for a voltage controlled switch, and then document all four parameters (Vt, Vh, VON, and VOFF) that may be used with those models along with a clear explanation of how LTspice chooses the limits it actually uses in a simulation. 

    I see no reason why LTspice accepts one set of PSpice parameters and not the other. Both are accepted by PSpice, and LTspice accepts the VSWITCH model type for PSpice compatibility, so LTspice should also accept both sets of PSpice model parameters. Especially when it is simple to convert from one to the other. 

    The goal, after all, is to allow LTspice to run PSpice models without modification! If I have to modify the PSpice model to use it with LTspice, then LTspice isn't really PSpice compatible.

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