Hi,
I believe I have found a bug in LTspice support for the PSpice VSWITCH model type.
I am trying to use an unencrypted PSpice model for the UC3843 provided by TI at UCCx8C43 Unencrypted PSpice Transient Model. This model has a couple of items that must be modified for use with LTspice; there are a few "^" characters used for exponentiation, and V3 generates a warning because it is missing a value of 0. Even with those changes (and several other minor mods) I am having little success running a boost converter circuit using this controller. So I decided to start simulating some of the subcircuits on there own to see what worked and what didn't.
One of the first function on the chip is the oscillator, described at the very beginning of the spice library file as ("..." added where lines were dropped):
.SUBCKT UCC28C43_STEADY COMP FB CS RTCT GND OUT VDD VREF
****OSCILLATOR*****
STOF1 8 GND RTCT GND SOSC
GBDISCH RTCT GND Value = { IF ( V(8,GND) < 2.5 & V(13,GND) > 2.5, 8.4M, 0 ) }
RPULL 8 VREF 100K
...
****REFERENCE*******
EBREF 13 GND Value = { IF ( V(19,GND) > 6, 5, 0 ) }
RREG 10 VREF 0.158
CREF VREF GND 1N
V3 13 10
...
.MODEL SOSC VSWITCH (RON=.01 ROFF=1MEG VT=1.45 VH=0.95) ; VT=1.45 set to match 53k @ 3.3n/10k
I created a standalone model of the oscillator circuit as a separate LTspice schematic. This file uses the definition of the G source and the voltage controlled switch identical to those defined in the TI library file.
This file runs at an extremely slow rate, simulating fs/s with many "Warning: Simulation tolerance relaxed to achieve convergence from..." messages generated and logged. The simulation never completes and has to be stopped manually.
To correct this I replaced the VSWITCH in the SOSC model definition with the LTspice equivalent SW. With this simple change the simulation runs to completion is a few seconds. The strange thing is the Expanded Netlist for both versions is exactly the same, showing SOSC defined as a SW model.
--- Expanded Netlist --- S1 0 CLK RTCT 0 SOSC V1 N001 0 DC=5 R2 VREF RTCT R=10000 R3 VREF N001 R=0.158 R1 VREF CLK R=100000 C1 RTCT 0 CAPACITANCE=3.3e-09 C2 VREF 0 CAPACITANCE=1e-09 GBDISCH RTCT 0 I=if((v(clk)<2.5)&(v(vref)>2.5),0.008400000000000001,0) .model SOSC SW(RON=0.01 ROFF=1000000 VT=1.45 VH=0.95) .end
The behavior of the circuit is very much different with the VSWITCH model type in the schematic even though both VSWITCH and SW produce the same Expanded Netlist. I believe this must be a bug.