Multiple sub-circuit definition with same name

Dear Markus,

How do you know this wasn't a problem in the past? Are these sub-circuits identical? If not, how would LTspice know which to choose?

All spice directives are put into the netlist in unspecifed order, thus they all appear in the same scope.

Either use unique names or move the auxiliary definitions into the sub-circuit definitions that use them.

Best Regards,
Mathias

Hi there,
thanks for the reply! 
I know that because this simulation runs smoothly when loaded into LTspice xvII (17.0.37.0) installation!
Just checked it with my old computer!

I have downloaded the complex models from the manufacturers website. Both of them.
Both components are from the same family, so the models use the some names and subcircuits.
When I got you right you are proposing that I should edit one of the models and rename all definitions and names that cause trouble.
Wow, that sounds awful. I will probably make mistakes and render that model useless.
These models are huge!

.subckt OPA322 IN+ IN- VCC VEE OUT
******************************************************
* MODEL DEFINITIONS:
.model BB_SW VSWITCH(Ron=50 Roff=1e12 Von=700e-3 Voff=0)
.model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=250e-3 Voff=0)
.model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=900e-3 Voff=800e-3)
.model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0)
.model R_NOISELESS RES(T_ABS=-273.15)
******************************************************
 

I_OS        ESDn MID 1F
I_B         21 MID 200F
V_GRp       58 MID 54
V_GRn       59 MID -56
V_ISCp      52 MID 65
V_ISCn      53 MID -70
V_ORn       51 VCLP -1.06
V11         57 50 0
V_ORp       49 VCLP 1.06
V12         56 48 0
V4          34 OUT 0
VCM_MIN     80 VEE_B -100M
VCM_MAX     81 VCC_B 100M
I_Q         VCC VEE 1.6M
V_OS        88 21 444.5U
Xi_nn       ESDn MID FEMT_0
Xi_np       MID 21 FEMT_0
Xe_n        ESDp 21 VNSE_0
C23         22 MID 1F  
R67         MID 22 R_NOISELESS 1MEG 
GVCCS4      22 MID VSENSE MID  -1U
C20         CLAMP MID 27.248N  
XVCCS_LIM_2 23 MID MID CLAMP VCCS_LIM_2_0
XVCCS_LIM_1 24 25 MID 23 VCCS_LIM_1_0
R66         MID CLAMP R_NOISELESS 1MEG 
R44         MID 23 R_NOISELESS 1MEG 
R65         26 MID R_NOISELESS 1 
XVCCS_LIM_ZO 27 MID MID 26 VCCS_LIM_ZO_0
R64         27 MID R_NOISELESS 204.1 
C22         27 28 7.958F  
R63         27 28 R_NOISELESS 10K 
R62         28 MID R_NOISELESS 1 
GVCCS3      28 MID 29 MID  -1
C21         30 MID 25F  
R61         29 30 R_NOISELESS 10K 
R58         29 31 R_NOISELESS 125.3K 
R57         31 MID R_NOISELESS 1 
GVCCS2      31 MID 32 MID  -2.31
C16         33 32 39.79U  
R51         32 MID R_NOISELESS 7.62K 
R50         32 33 R_NOISELESS 10K 
Rdummy      MID 34 R_NOISELESS 4K 
Rx          34 26 R_NOISELESS 40K 
Rdc         33 MID R_NOISELESS 1 
G_Aol_Zo    33 MID CL_CLAMP 34  -181.82
R56         MID 35 R_NOISELESS 1.058K 
C15         35 36 3.009P 
R55         36 35 R_NOISELESS 100MEG 
GVCCS1      36 MID VEE_B MID  -954.2M
R54         MID 36 R_NOISELESS 1 
R80         MID 37 R_NOISELESS 1.058K 
C14         37 38 3.009P 
R79         38 37 R_NOISELESS 100MEG 
G_adjust    38 MID VCC_B MID  -954.2M
R78         MID 38 R_NOISELESS 1 
R49         MID 39 R_NOISELESS 1 
G_2         39 MID 40 MID  -555.6
R2b         MID 40 R_NOISELESS 180.3K 
C1b         40 41 17.68F 
R1b         41 40 R_NOISELESS 100MEG 
R48         MID 41 R_NOISELESS 1 
GVCCS9      41 MID 42 MID  -1
R2a         MID 42 R_NOISELESS 180.3K 
C1a         42 43 17.68F 
R1a         43 42 R_NOISELESS 100MEG 
G_1         43 MID ESDp MID  -5.556M
Rsrc        MID 43 R_NOISELESS 1 
S5          VEE ESDp VEE ESDp  S_VSWITCH_1
S4          VEE ESDn VEE ESDn  S_VSWITCH_2
S2          ESDn VCC ESDn VCC  S_VSWITCH_3
S3          ESDp VCC ESDp VCC  S_VSWITCH_4
C28         44 MID 1P 
R77         45 44 R_NOISELESS 100 
C27         46 MID 1P 
R76         47 46 R_NOISELESS 100 
R75         MID 48 R_NOISELESS 1 
GVCCS8      48 MID 49 MID  -1
R74         50 MID R_NOISELESS 1 
GVCCS7      50 MID 51 MID  -1
XIQPos      VIMON MID MID VCC VCCS_LIMIT_IQ_0
XIQNeg      MID VIMON VEE MID VCCS_LIMIT_IQ_0
C_DIFF      ESDp ESDn 5P 
XCL_AMP     52 53 VIMON MID 54 55 CLAMP_AMP_LO_0
SOR_SWp     CLAMP 56 CLAMP 56  S_VSWITCH_5
SOR_SWn     57 CLAMP 57 CLAMP  S_VSWITCH_6
XGR_AMP     58 59 60 MID 61 62 CLAMP_AMP_HI_0
R39         58 MID R_NOISELESS 1T 
R37         59 MID R_NOISELESS 1T 
R42         VSENSE 60 R_NOISELESS 1M 
C19         60 MID 1F 
R38         61 MID R_NOISELESS 1 
R36         MID 62 R_NOISELESS 1 
R40         61 63 R_NOISELESS 1M 
R41         62 64 R_NOISELESS 1M 
C17         63 MID 1F 
C18         MID 64 1F 
XGR_SRC     63 64 CLAMP MID VCCS_LIM_GR_0
R21         54 MID R_NOISELESS 1 
R20         MID 55 R_NOISELESS 1 
R29         54 65 R_NOISELESS 1M 
R30         55 66 R_NOISELESS 1M 
C9          65 MID 1F 
C8          MID 66 1F 
XCL_SRC     65 66 CL_CLAMP MID VCCS_LIM_4_0
R22         52 MID R_NOISELESS 1T 
R19         MID 53 R_NOISELESS 1T 
XCLAWp      VIMON MID 67 VCC_B VCCS_LIM_CLAWP_0
XCLAWn      MID VIMON VEE_B 68 VCCS_LIM_CLAWN_0
R12         67 VCC_B R_NOISELESS 1K 
R16         67 69 R_NOISELESS 1M 
R13         VEE_B 68 R_NOISELESS 1K 
R17         70 68 R_NOISELESS 1M 
C6          70 MID 1F 
C5          MID 69 1F 
G2          VCC_CLP MID 69 MID  -1M
R15         VCC_CLP MID R_NOISELESS 1K 
G3          VEE_CLP MID 70 MID  -1M
R14         MID VEE_CLP R_NOISELESS 1K 
XCLAW_AMP   VCC_CLP VEE_CLP VOUT_S MID 71 72 CLAMP_AMP_LO_0
R26         VCC_CLP MID R_NOISELESS 1T 
R23         VEE_CLP MID R_NOISELESS 1T 
R25         71 MID R_NOISELESS 1 
R24         MID 72 R_NOISELESS 1 
R27         71 73 R_NOISELESS 1M 
R28         72 74 R_NOISELESS 1M 
C11         73 MID 1F 
C10         MID 74 1F 
XCLAW_SRC   73 74 CLAW_CLAMP MID VCCS_LIM_3_0
H2          47 MID V11 -1
H3          45 MID V12 1
C12         SW_OL MID 100P 
R32         75 SW_OL R_NOISELESS 100 
R31         75 MID R_NOISELESS 1 
XOL_SENSE   MID 75 46 44 OL_SENSE_0
S1          33 32 SW_OL MID  S_VSWITCH_7
H1          76 MID V4 1K
S7          VEE OUT VEE OUT  S_VSWITCH_8
S6          OUT VCC OUT VCC  S_VSWITCH_9
R11         MID 77 R_NOISELESS 1T 
R18         77 VOUT_S R_NOISELESS 100 
C7          VOUT_S MID 1N 
E5          77 MID OUT MID  1
C13         VIMON MID 1N 
R33         76 VIMON R_NOISELESS 100 
R10         MID 76 R_NOISELESS 1T 
R47         78 VCLP R_NOISELESS 100 
C24         VCLP MID 100P 
E4          78 MID CL_CLAMP MID  1
R46         MID CL_CLAMP R_NOISELESS 1K 
G9          CL_CLAMP MID CLAW_CLAMP MID  -1M
R45         MID CLAW_CLAMP R_NOISELESS 1K 
G8          CLAW_CLAMP MID 22 MID  -1M
R43         MID VSENSE R_NOISELESS 1K 
G15         VSENSE MID CLAMP MID  -1M
C4          24 MID 1F 
R9          24 79 R_NOISELESS 1M 
R7          MID 80 R_NOISELESS 1T 
R6          81 MID R_NOISELESS 1T 
R8          MID 79 R_NOISELESS 1 
XVCM_CLAMP  82 MID 79 MID 81 80 VCCS_EXT_LIM_0
E1          MID 0 83 0  1
R89         VEE_B 0 R_NOISELESS 1 
R5          84 VEE_B R_NOISELESS 1M 
C3          84 0 1F 
R60         83 84 R_NOISELESS 1MEG 
C1          83 0 1 
R3          83 0 R_NOISELESS 1T 
R59         85 83 R_NOISELESS 1MEG 
C2          85 0 1F 
R4          VCC_B 85 R_NOISELESS 1M 
R88         VCC_B 0 R_NOISELESS 1 
G17         VEE_B 0 VEE 0  -1
G16         VCC_B 0 VCC 0  -1
R_PSR       86 82 R_NOISELESS 1K 
G_PSR       82 86 37 35  -1M
R2          25 ESDn R_NOISELESS 1M 
R1          86 87 R_NOISELESS 1M 
R_CMR       88 87 R_NOISELESS 1K 
G_CMR       87 88 39 MID  -1M
C_CMn       ESDn MID 4P 
C_CMp       MID ESDp 4P 
R53         ESDn MID R_NOISELESS 1T 
R52         MID ESDp R_NOISELESS 1T 
R35         IN- ESDn R_NOISELESS 10M 
R34         IN+ ESDp R_NOISELESS 10M 
 
.MODEL S_VSWITCH_1 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=100M)
.MODEL S_VSWITCH_2 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=100M)
.MODEL S_VSWITCH_3 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=100M)
.MODEL S_VSWITCH_4 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=100M)
.MODEL S_VSWITCH_5 VSWITCH (RON=10M ROFF=1T VON=10M VOFF=0)
.MODEL S_VSWITCH_6 VSWITCH (RON=10M ROFF=1T VON=10M VOFF=0)
.MODEL S_VSWITCH_7 VSWITCH (RON=1M ROFF=1T VON=500M VOFF=100M)
.MODEL S_VSWITCH_8 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=100M)
.MODEL S_VSWITCH_9 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=100M)
 
.ENDS OPA322
*
.SUBCKT FEMT_0  1 2
.PARAM FLWF=1E-3
.PARAM NLFF=0.6
.PARAM NVRF=0.6
.PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164}
.PARAM RNVF={1.184*PWR(NVRF,2)}
.MODEL DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVNF
D2 8 0 DVNF
E1 3 6 7 8 {GLFF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNVF}
R5 5 0 {RNVF}
R6 3 4 1E9
R7 4 0 1E9
G1 1 2 3 4 1E-6
.ENDS
*
 

.SUBCKT VNSE_0  1 2
.PARAM FLW=10
.PARAM NLF=55.5
.PARAM NVR=7.11
.PARAM GLF={PWR(FLW,0.25)*NLF/1164}
.PARAM RNV={1.184*PWR(NVR,2)}
.MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVN
D2 8 0 DVN
E1 3 6 7 8 {GLF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNV}
R5 5 0 {RNV}
R6 3 4 1E9
R7 4 0 1E9
E3 1 2 3 4 1
.ENDS
*
 

.SUBCKT VCCS_LIM_2_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 3.74E-2
.PARAM IPOS = 280E-3
.PARAM INEG = -280E-3
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
 

.SUBCKT VCCS_LIM_1_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1E-4
.PARAM IPOS = .5
.PARAM INEG = -.5
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
 

.SUBCKT VCCS_LIM_ZO_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 50
.PARAM IPOS = 6E3
.PARAM INEG = -6E3
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
 

.SUBCKT VCCS_LIMIT_IQ_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1E-3
G1 IOUT- IOUT+ VALUE={IF( (V(VC+,VC-)<=0),0,GAIN*V(VC+,VC-) )}
.ENDS
*
 

.SUBCKT CLAMP_AMP_LO_0  VC+ VC- VIN COM VO+ VO-
.PARAM G=1
GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ENDS
*
 

.SUBCKT CLAMP_AMP_HI_0  VC+ VC- VIN COM VO+ VO-
.PARAM G=10
GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ENDS
*
 

.SUBCKT VCCS_LIM_GR_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 600E-3
.PARAM INEG = -600E-3
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
 

.SUBCKT VCCS_LIM_4_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 220E-3
.PARAM INEG = -220E-3
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS VCCS_LIM_4_0 
*
 

.SUBCKT VCCS_LIM_CLAWP_0  VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {ABS(V(VC+,VC-))} =
+(0, 1E-5)
+(21.4339, 3.55E-4)
+(39.5385, 7.67E-4)
+(50.8008, 1.20E-3)
+(55.9294, 1.55E-3)
+(59.0736, 1.90E-3)
+(60.7526, 2.18E-3)
+(62.0000, 2.40E-3)
+(63.4085, 2.74E-3)
+(65.0000, 2.75E-3)
.ENDS VCCS_LIM_CLAWP_0 
*
 

.SUBCKT VCCS_LIM_CLAWN_0  VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {ABS(V(VC+,VC-))} =
+(0.0000, 1E-5)
+(9.8642, 1.31E-4)
+(21.4339, 3.16E-4)
+(39.5483, 6.51E-4)
+(50.8008, 9.00E-4)
+(60.7526, 1.21E-3)
+(63.0727, 1.31E-3)
+(67.8349, 1.59E-3)
+(70.4602, 1.96E-3)
.ENDS VCCS_LIM_CLAWN_0 
*
 

.SUBCKT VCCS_LIM_3_0  VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 108E-3
.PARAM INEG = -108E-3
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS VCCS_LIM_3_0 
*
 

.SUBCKT OL_SENSE_0  COM SW+ OLN  OLP
GSW+ COM SW+ VALUE = {IF((V(OLN,COM)>10E-3 | V(OLP,COM)>10E-3),1,0)}
.ENDS
*
 

.SUBCKT VCCS_EXT_LIM_0  VIN+ VIN- IOUT- IOUT+ VP+ VP-
.PARAM GAIN = 1
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}
.ENDS
*

Hi MarkusB ,

Zip up your schematic and libraries and upload and I will see about possible solutions.

mike

No, what I meant is to simply move line 208 to the end of the file, which is what the author of the model should have done.

Best Regards,
Mathias

what was your solution?

See ez.analog.com/.../there-is-more-than-one-sub-circuit-definition-with-this-name-which-is-ill-formed

i also meet this problem. and when i change the name which is repetition the sim is runing successful.