Dear Sirs at Analog:
At my attempt to simulate a simple circuit (Half bridge Zero-Current Resonant inverter), with inductive coupleted load, the simulation is heavily delays (with no errors) at a specific time-step.
The net list of the circuit is:
* Z:\ltspice\PROJECTS\2-THYRISTOR-2-DIODE-RESONAND-HB-INVERTER.asc
* Generated by LTspice 24.1.8 for Windows.
V1 N001 N004 320 Rser=0
LP1 V_PRI N003 { L_RES } Rser=0.000
X§X1 - U1G NC_01 NC_02 U3C U3G U4C U4G NC_03 NC_04 0 U6G BEHAVORAL-PUSE-GEN params: ZLEVEL=0 ONELEVEL=100 TDELAY=0.01 DT=0.25m TRISE=1n TFALL=1n D=0.01 RG=1 PERIOD=0.2M NCYCLES=100k
X§UD1 N004 V_PRI DIODE-GENERIC VMAX={ 1400 } IMAX={ 500 } TRR={ 10N }
L_FILT + N001 1m Rser=0.001
X§UD3 V_PRI N001 DIODE-GENERIC VMAX={ 1400 } IMAX={ 500 } TRR={ 10N }
C1 + - 10m
C_SNUB2 V_PRI + { C_RES }
C_SNUB3 - V_PRI { C_RES }
L_FILT1 - N004 1m Rser=0.001
RLP1 0 N003 1m
X§X2 + U6G 0 THYRISTOR-TT-CIR params: BF_NPN={ BF_NPN } BF_PNP={ BF_PNP } BR_NPN={ BR_NPN } BR_PNP={ BR_PNP } TF={ TF } TR={ TR } IS={ IS } LOOP_GAIN={ LOOP_GAIN } RATIO={ RATIO } RE={ RE } C_AC={ C_AC } BVCBO={ BVCBO } R_GATE_CATHODE={ R_GATE_CATHODE }
X§X3 0 U1G - THYRISTOR-TT-CIR params: BF_NPN={ BF_NPN } BF_PNP={ BF_PNP } BR_NPN={ BR_NPN } BR_PNP={ BR_PNP } TF={ TF } TR={ TR } IS={ IS } LOOP_GAIN={ LOOP_GAIN } RATIO={ RATIO } RE={ RE } C_AC={ C_AC } BVCBO={ BVCBO } R_GATE_CATHODE={ R_GATE_CATHODE }
LS1 N002 0 { L_RES * N * N } Rser=0.000
R_LOAD N002 0 10
* block symbol definitions
.subckt BEHAVORAL-PUSE-GEN P1C P1G P2C P2G P3C P3G P4C P4G P5C P5G P6C P6G
R1 P1G VP1 { RG }
V4 VP4 P4C PULSE({ ZLEVEL} {ONELEVEL} { TDELAY+PERIOD/2 } { TRISE } { TFALL } { D*PERIOD } { PERIOD } { NCYCLES })
X§X1 P1G 0 P1C PCB-TERMINAL-BLOCK3
X§X4 P4C 0 P4G PCB-TERMINAL-BLOCK3
X§X5 P5C 0 P5G PCB-TERMINAL-BLOCK3
X§X6 P6C 0 P6G PCB-TERMINAL-BLOCK3
X§X2 P2G 0 P2C PCB-TERMINAL-BLOCK3
V3 VP3 P3C PULSE({ ZLEVEL} {ONELEVEL} { TDELAY } { TRISE } { TFALL } { D*PERIOD } { PERIOD } { NCYCLES })
X§X3 P3G 0 P3C PCB-TERMINAL-BLOCK3
R2 P2G VP2 { RG }
R3 P3G VP3 { RG }
R4 P4G VP4 { RG }
R5 P5G VP5 { RG }
R6 P6G VP6 { RG }
V1 VP1 P1C PULSE({ ZLEVEL} {ONELEVEL} { TDELAY + DT } { TRISE } { TFALL } { D*PERIOD } { PERIOD } { NCYCLES })
V2 VP2 P2C PULSE({ ZLEVEL} {ONELEVEL} { TDELAY + DT } { TRISE } { TFALL } { D*PERIOD } { PERIOD } { NCYCLES })
V5 VP5 P5C PULSE({ ZLEVEL} {ONELEVEL} { TDELAY+PERIOD/2 + DT } { TRISE } { TFALL } { D*PERIOD } { PERIOD } { NCYCLES })
V6 VP6 P6C PULSE({ ZLEVEL} {ONELEVEL} { TDELAY+PERIOD/2 + DT } { TRISE } { TFALL } { D*PERIOD } { PERIOD } { NCYCLES })
.PARAMS GMIN=1.0E-09 R_ISOL={ 1 / GMIN }
.ends BEHAVORAL-PUSE-GEN
.subckt THYRISTOR-TT-CIR A G C
Q3 N007 N006 N003 0 QP OFF
R_GATE_CATHODE C N010 { R_GATE_CATHODE }
R_ANODE N006 A { 100 * R_GATE_CATHODE }
Q6 N008 N010 N012 0 QN OFF
R10 N005 A { RE }
R11 N004 A { RE }
R12 N003 A { RE }
R13 C N012 { RE }
R14 C N013 { RE }
R15 C N014 { RE }
D1 A N001 D
D2 N001 N002 D
D3 N002 N006 D
D6 N015 C D
C_AC N009 N010 { C_AC }
Q2 N007 N006 N004 0 QP OFF
Q1 N007 N006 N005 0 QP OFF
Q4 N008 N010 N014 0 QN OFF
Q5 N008 N010 N013 0 QN OFF
D5 N011 N015 D
D7 N010 N011 D
D4 N007 N010 D
D8 N006 N008 D
D9 G N010 D
R_AC N009 N006 { 5K * R_GATE_CATHODE }
.MODEL D D
.MODEL QP PNP (TF={ TF } TR={ TR } CJC=1PF CJE=1P XTB=2.5 IS={ IS } ISE=1.0E-08 NE=2 BF={ BF_PNP } BR={ BR_PNP } ISC=1.0E-09 NC=2 RE={ RE } BVCBO={ BVCBO } )
.MODEL QN NPN (TF={ TF } TR={ TR } CJC=1PF CJE=1P XTB=2.5 IS={ IS } ISE=1.0E-08 NE=2 BF={ BF_NPN } BR={ BR_NPN } ISC=1.0E-09 NC=2 RE={ RE } BVCBO={ BVCBO } )
.param BF_PNP={ LOOP_GAIN * ( 1 - RATIO ) }
.param BF_NPN={ LOOP_GAIN * ( 1 + RATIO ) }
.param RATIO={ RATIO }
.PARAMS BR_PNP={ BR_PNP }
.PARAMS BR_NPN={ BR_NPN }
.ends THYRISTOR-TT-CIR
.subckt PCB-TERMINAL-BLOCK3 1 2 3
R1 1 2 { R_ISOL }
R2 2 3 { R_ISOL }
.PARAMS R_ISOL={ 1 / GMIN }
.ends PCB-TERMINAL-BLOCK3
.tran 0 1k 0
.lib TMP.lib
.param C_RES=150u L_RES=1m N=1
.PARAMS VMAX=2000 IMAX=300 TRR=70N
.PARAMS BF_NPN=100 BF_PNP=5 BR_NPN=1.1 BR_PNP=1.1 TF=10n TR=10n IS=1P LOOP_GAIN=100 RATIO=0.05 RE=0.001 C_AC=10P BVCBO=1600 R_GATE_CATHODE=5
K LP1 LS1 0.9
.backanno
.end
I assume that there is a convergence problem in the core (Non - Linear solver) of software.
I am weighting for your answer.
My Best Regards
Antony Theodorakis
