AD8000 .cir emulation not working in LTSPICE

Robz  Before we start troubleshooting the model, I want to make sure your circuit is behaving as expected with an ideal opamp.

/cfs-file/__key/communityserver-discussions-components-files/1020/Basic-Circuit-with-ideal-opamp.asc

I've redrawn your schematic, with the following changes:

- I've replaced the AD8000 with an ideal opamp

- I've replaced the Rser in the input voltage with an actual resistor - just helps me to visualize.

- I've remove supply bypass caps - not needed for this sim, just trying to simplify as much as I can.

I'm using an input signal with a lower frequency, just to make sure I understand the behavior of the circuit.

The opamp DC bias at In+ is set by the 27k resistor divider to Vcc/2 - that looks fine.

The opamp is going to drive the DC bias of the output to 4.4V - since it's trying to drive that 430 resistor divider connecting to IN- to Vcc/2, to drive the opamp inputs to the same voltage.

Can we work this this simpler schematic to ensure it's behaving as expected before switching out to the more complex macromodel?  One thing that is going to give us trouble when we switch this ideal model with a more realistic model is that the opamp is trying to drive the output to the supply rail.  One possibility is to replace the GND of the 430 resistor divider with VCM = 2.2V?

Robz  Before we start troubleshooting the model, I want to make sure your circuit is behaving as expected with an ideal opamp.

/cfs-file/__key/communityserver-discussions-components-files/1020/Basic-Circuit-with-ideal-opamp.asc

I've redrawn your schematic, with the following changes:

- I've replaced the AD8000 with an ideal opamp

- I've replaced the Rser in the input voltage with an actual resistor - just helps me to visualize.

- I've remove supply bypass caps - not needed for this sim, just trying to simplify as much as I can.

I'm using an input signal with a lower frequency, just to make sure I understand the behavior of the circuit.

The opamp DC bias at In+ is set by the 27k resistor divider to Vcc/2 - that looks fine.

The opamp is going to drive the DC bias of the output to 4.4V - since it's trying to drive that 430 resistor divider connecting to IN- to Vcc/2, to drive the opamp inputs to the same voltage.

Can we work this this simpler schematic to ensure it's behaving as expected before switching out to the more complex macromodel?  One thing that is going to give us trouble when we switch this ideal model with a more realistic model is that the opamp is trying to drive the output to the supply rail.  One possibility is to replace the GND of the 430 resistor divider with VCM = 2.2V?

Why didn't you just use the AD8000 model, the circuit is just as simple as using the 5532.

The interface on LTSpice is not exactly intuitive, so its faster for you, someone who knows the tricks, to add the AD8000 than for a new user, me, to set up an alternative op amp.

If you can't add the AD8000 and get it to work, what hope do I have?

I also need to test from 100KHz to 160 MHz, and a 0.2uV input signal, that is the goal, anything less is worthless, and as this isn't rocket science, it really should work.

I've edited your model to use the AD8000.cir model, and there is an output, but very attenuated.

Basic Circuit with ideal opamp - AD8000 added 1.asc

It seems unstable, I get different results each time I click a sample point, this one shows the 200nV inout, but at 400nV p-p, and the output is just a few nV.

Robz I'm peeling layers of an onion.  You have a simulation that isn't working, and I'm trying to help you figure out why.

You are correct - adding a part like the AD8000 is not intuitive - we have lots of op amps included in the LTspice library that would be easy to add to a schematic, but the AD8000 isn't one of them.  So that is one of the things that's making this complicated - I understand the frustration.

But I'm also trying to understand the circuit you've built, and what it's supposed to be doing.  The original schematic you attached had R3 set to an incorrect value, I believe, so that was one issue.  I'm also trying to understand if you're going to violate the limits of the opamp that are dictated by the supply voltages that are being fed to the opamp - that's another potential issue.

If we can get something working the way you expect with an ideal opamp model, it gets us closer to feeling good about the circuit topology overall - then we can examine if things work as expected when we switch out the ideal opamp with the AD8000.

Robz  what you're seeing here was puzzling to me - took a while to get an answer for...

The compression feature is behaving poorly with such a low voltage signal.  Go into Tools -> Settings, and in the Compression tab, uncheck "Enable 1st Order Compression."

You can also add a ".options plotwinsize=0" directive to your schematic to override this setting.  See "Compression" in the LTspice Help Manual for more information.

I don't think this will fix everything, but it'll fix that jagged output you're seeing.

It's the dramatically reduced gain that is the problem, because it means we can be concerned that the AD8000 doesn't work, or that ADI are unable to produce a working simulation file, neither of which gives us as a company, enough confidence to use ADI products

It looks like LTSpice is unable to simulate the AD8000 (bad ad800.cir file?), and above a few 100 KHz also fails.  Even with a gain of +10 set for Rf/Rg, the gain isn't correct.   (also, clicking on inputs and outputs more than once causes a big change in values, like its unstable)

Robz R3 and R4 are serving as a voltage divider - the output of the amp will *try* to drive to a voltage to ensure that the inverting input voltage is equal to the non-inverting input voltage.

You have R4 connected to ground, and R3 connected to the output of the amp - and the op amp will do whatever it takes to get that node between R3 and R4 to equal the voltage on the other input of the op amp.

In the case of R3 = R4, and R4 connected to ground - the opamp will attempt to drive the output to 4.4V, which will result in 2.2V at the inverting input.

In your R3 = 357, R4 = 40 case, the op amp will attempt to drive the output to 22V, to result in 2.2V at the inverting input.

Neither of these cases is actually achievable with any real op amp.  You are providing a positive supply of 4.4V - the opamp will not be able to drive the output to 4.4V, and then also amplify an AC signal on top of that.  This is clipping the op amp.

This is why I think it's really useful to start with an ideal op amp model in your simulation.  It's really hard to troubleshoot an op amp macromodel when you haven't proven that the circuit works fine with an ideal opamp.

For your circuit above, do the following:

1) apply a 2.2V voltage source to R4 (where you currently have ground)

2) add a net name to the wire that's connected to the output of the op amp, and probe that on the waveform viewer.  It's hard to see what's going on when you probe the other side of C1.  Probe the op amp side of C1 and see what that looks like.

Anne, as this is a single-rail implementation, I understand that it's required to bias the non-inverting input at VCC/2 to avoid the RF input driving the input negative.
The rest of the circuit as regards to Rf/Rg is as per page 5 of the AD8000  datasheet.

How do you suggest the AD8000 be connected to achieve the required gain with single rail operation?